M95640-RMN6TP STMicroelectronics, M95640-RMN6TP Datasheet - Page 12

IC EEPROM 64KBIT 5MHZ 8SOIC

M95640-RMN6TP

Manufacturer Part Number
M95640-RMN6TP
Description
IC EEPROM 64KBIT 5MHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheets

Specifications of M95640-RMN6TP

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
5MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8698-2
M95640-RMN6TP

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Operating features
4
4.1
4.1.1
4.1.2
4.1.3
12/44
Operating features
Supply voltage (V
Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable V
within the specified [V
Table
instruction and, for a Write instruction, until the completion of the internal write cycle (t
order to secure a stable DC supply voltage, it is recommended to decouple the V
a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V
pins.
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
reaches the internal threshold voltage (this threshold is defined in DC characteristics tables
13, 14,
When V
When V
Power mode. The device must not be accessed until V
voltage within the specified [V
Table
Power-up conditions
When the power supply is turned on, V
time, the Chip Select (S) line is not allowed to float but should follow the V
therefore recommended to connect the S line to V
Figure
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The V
defined in
in the Standby Power mode
deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S))
Status register values:
10). This voltage must remain stable and valid until the end of the transmission of the
10.
CC
3).
15
CC
CC
voltage has to rise continuously from 0 V up to the minimum V
the Write Enable Latch (WEL) bit is reset to 0
the Write In Progress (WIP) bit is reset to 0
the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
Table
and
passes over the POR threshold, the device is reset and in the following state:
passes over the POR threshold, the device is reset and enters the Standby
16
8,
as V
Table 9
CC
RES
(min), V
CC
).
and
CC
)
Doc ID 5711 Rev 12
Table 10
CC
(min), V
CC
(max)] range must be applied (see
CC
CC
and the rise time must not vary faster than 1 V/µs.
continuously rises from V
(max)] range defined in
CC
via a suitable pull-up resistor (see
CC
reaches a valid and stable V
M95320, M95320-W, M95320-R
Table
SS
Table
to V
CC
8,
CC
operating voltage
CC
CC
Table 9
8,
voltage. It is
/V
. During this
Table 9
CC
SS
CC
package
voltage
line with
and
CC
W
CC
and
). In

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