DS4510U-15/T&R Maxim Integrated, DS4510U-15/T&R Datasheet - Page 6

• Manufacturer Part Number: DS4510U-15/T&R
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: DS4510r

Specifications of DS4510U-15/T&R

• Number Of Voltages Monitored: 1
• Undervoltage Threshold: 4 V
• Overvoltage Threshold: 4.24 V
• Output Type: Active Low, Open Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 1100 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-10
• Chip Enable Signals: No
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Voltage - Min: 2.7 V
• Part # Aliases: 90-4510U-Y15

The DS4510 contains a CPU supervisor, four program-
mable I/O pins, and a 64-byte EEPROM memory. All
functions are configurable or controllable through an
industry-standard I
isters that are likely to require frequent modification are
implemented using SRAM-shadowed EEPROM (SEEP-
ROM) memory. This memory is configurable to act as
volatile SRAM or NV EEPROM by adjusting the SEE bit
in the Config register. Configuring the SEEPROM as
SRAM eliminates the EEPROM write time and allows
infinite write cycles to these registers. Configuring the
registers as EEPROM allows the application to change
the power-on values that are recalled during power-up.
The timeout period is adjusted by writing the reset
delay register (SEEPROM). The delay for each setting
is shown in the CPU Supervisor AC Electrical
Characteristics. If the SEE bit is set, changes are writ-
ten to SRAM. On power-up the last value written to the
EEPROM is recalled. The I
vate the RST by setting the SWRST bit in the Config
register. This bit automatically returns to zero after the
timeout period. The Config register also contains the
ready, trip point, and reset status bits. The ready bit
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
6
_____________________________________________________________________
Programmable CPU Supervisor
2
C-compatible bus. DS4510 NV reg-
GND
SDA
SCL
V
A0
CC
Detailed Description
2
C bus is also used to acti-
INTERFACE
64 BYTES
MEMORY
EEPROM
2-WIRE
USER
V
CC
REFERENCE
INTERNAL
VOLTAGE
NONVOLATILE I/O LATCHES
V
CC
4 BIDIRECTIONAL
I/O
PULLUP ENABLE (F0h)
X
CONTROL (F4h-F7h)
I/O STATUS (F8h)
determines if the power-on reset level of the DS4510 is
surpassed by V
is above V
in its active state.
Note: The RST pin is an open-drain output, therefore an
external pullup resistor must be used to realize high
logic levels.
Each programmable I/O
collector output, and a selectable internal pullup resis-
tor. The DS4510 stores changes to the I/O
SEEPROM memory. Using the SEEPROM as SRAM is
conducive to applications such as I/O expansion that
generally require fast access times and frequent modi-
fication of the I/O
behave as EEPROM allows the modification of the
power-on state of the I/O
I/O
(typically), which is when the last value programmed is
recalled from EEPROM. On power-down, the I/O
is maintained until V
The internal pullups for each I/O
the pullup-enable register (F0h). Similarly, the individual
I/O
X
X
pins are high impedance until V
control registers (F4h to F7h) adjust the pulldown
PROGRAMMABLE
CCTP
RESET
TIMER
Programmable NV Digital I/O Pins
4x
DS4510
, and the reset status bit is set if RST is
CC
X
. The trip point bit determines if V
CC
pin. Configuring the SEEPROM to
drops below 1.9V (typically).
Functional Diagram
R
P
X
V
CC
pin contains an input, open-
X
pin. During power-up the
X
4 NV
I/O PINS
RST
pin are controlled by
CC
exceeds 2.0V
X
X
pin in
state
CC