NAND128W3A2BN6E NUMONYX, NAND128W3A2BN6E Datasheet
NAND128W3A2BN6E
Specifications of NAND128W3A2BN6E
497-5037
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NAND128W3A2BN6E Summary of contents
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... Byte/264 Word Page, 1.8V/3V, NAND Flash Memories FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES – Gbit memory array – Mbit spare area – Cost effective solutions for mass storage applications NAND INTERFACE – x16 bus width – Multiplexed Address/ Data – ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 1. Product List Reference NAND128-A NAND256-A NAND512-A NAND01G-A 2/56 Part Number NAND128R3A NAND128W3A NAND1282R4A NAND128W4A NAND256R3A NAND256W3A NAND256R4A NAND256W4A NAND512R3A NAND512W3A NAND512R4A NAND512W4A NAND01GR3A NAND01GW3A NAND01GR4A NAND01GW4A ...
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... Figure 8. FBGA63 Connections, x8 devices (Top view through package Figure 9. FBGA63 Connections, x16 devices (Top view through package MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inputs/Outputs (I/O0-I/O7 Inputs/Outputs (I/O8-I/O15 Address Latch Enable (AL Command Latch Enable (CL Chip Enable (E) ...
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... Table 8. Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DEVICE OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11.Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12.Pointer Operations for Programming Read Memory Array Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Read Sequential Row Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13.Read (A,B,C) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14.Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15.Sequential Row Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 16 ...
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Figure 23.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data 49 Figure 43.VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . ...
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... ST Sales office. For information on how to order these options refer to Table 28., Ordering Information vices are shipped from the factory with Block 0 al- ways valid and the memory content bits, in valid blocks, erased to ’1’. See Table 2., Product vices available in the family. ...
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... NAND01GW3A NAND01G-A 1Gbit NAND01GR4A x16 NAND01GW4A Figure 2. Logic Diagram NAND Flash 8/56 Page Block Memory Operating Size Size Array Voltage 1.7 to 1.95V 512+16 16K+512 Bytes Bytes 2.7 to 3.6V 32 Pages x 1024 Blocks 1.7 to 1.95V 256+8 8K+256 Words Words 2.7 to 3.6V 1.7 to 1.95V ...
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... Figure 3. Logic Block Diagram Address Register/Counter Command Interface E Logic WP R Command Register NAND128-A, NAND256-A, NAND512-A, NAND01G-A NAND Flash Memory Array P/E/R Controller, High Voltage Generator Page Buffer Cache Register Y Decoder I/O Buffers & Latches RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16 AI07561b 9/56 ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 4. TSOP48 and WSOP48 Connections, x8 devices NAND Flash (x8 ...
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Figure 6. FBGA55 Connections, x8 devices (Top view through package NAND128-A, NAND256-A, NAND512-A, NAND01G ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 7. FBGA55 Connections, x16 devices (Top view through package 12/ ...
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Figure 8. FBGA63 Connections, x8 devices (Top view through package NAND128-A, NAND256-A, NAND512-A, NAND01G ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 9. FBGA63 Connections, x16 devices (Top view through package I/ 14/56 3 ...
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... MEMORY ARRAY ORGANIZATION The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data ...
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... Refer to the teristics value of the pull-up resistor. V Supply Voltage supply to the internal core of the memory device the main power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever V 1.5V (for 1.8V devices) to protect the device from any involuntary program/erase during power-tran- ) ...
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... When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be al- tered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 6. Address Insertion, x8 Devices Bus Cycle I/O7 I/ A16 A15 2 rd A24 A23 3 th( Note set Low or High ...
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COMMAND SET All bus write operations to the device are interpret the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. ...
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... Figure 11.) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory array (they se- lect the most significant column address). The Read A and Read B commands act as point- ers to the main memory area. Their use depends on the bus width of the device ...
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... Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Operations section. Once the area (main or spare) has been selected using the Read A, Read B or Read C commands four bus cycles (for 512Mb and 1Gb devices) or three bus cycles (for 128Mb ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 14. Read Block Diagrams Read A Command, X8 Devices Area A (2nd half Page) (1st half Page) A9-A26 (1) A0-A7 Read B Command, X8 Devices Area A (2nd half Page) (1st half Page) A9-A26 (1) ...
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... Page Program The Page Program operation is the standard oper- ation to program data to the memory array. The main area of the memory array is pro- grammed by page, however partial page program- ming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be programmed. ...
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... The Copy Back Program operation does not re- quire external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is up- dated and the rest of the block needs to be copied to the newly assigned block ...
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... Interface and Status Register. If the Reset command is issued during any operation, the op- eration will be aborted was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. NAND128-A, NAND256-A, NAND512-A, NAND01G-A are required to input the block address ...
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... P/E/R Con- troller. The Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to ‘0’ the oper- ation has completed successfully. SR5, SR4, SR3, SR2 and SR1 are Reserved. ...
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Table 11. Status Register Bits Bit Name SR7 Write Protection Program/ Erase/ Read SR6 Controller SR5, SR4, Reserved SR3, SR2, SR1 SR0 Generic Error Read Electronic Signature The device contains a Manufacturer Code and De- vice Code. To read these ...
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... Enable Don’t Care disabled), the device will automatically enter Sequential Row Read mode (Automatic Memory Download) after the power-up sequence, and start reading Page 0, Page 1, etc., until the last memory location is reached, each new page being accessed after a time t BLBH1 ...
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... Collection, a Wear-Leveling Algorithm and an Er- ror Correction Code, to extend the number of pro- gram and erase cycles and increase the data retention. To help integrate a NAND memory into an applica- tion ST Microelectronics can provide: A Demo board with NAND simulation software for PCs File System OS Native reference software, which supports the basic commands of file management ...
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... After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further pro- gram operations it is recommended to implement a Garbage Collection algorithm Garbage Col- lection software the valid pages are copied into a ...
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First Level Wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles Second Level Wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequently- changed ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles per block are shown in ble 14. Table 14. Program, Erase Times and Program Erase Endurance Cycles ...
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DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- rived from tests performed ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 18. DC Characteristics, 1.8V Devices Symbol Parameter I DD1 Operating I Current DD2 I DD3 Stand-By Current (CMOS) 128Mb, 256Mb, 512Mb devices I DD5 Stand-By Current (CMOS) 512Mb and 1Gb Dual Die devices I Input ...
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Table 19. DC Characteristics, 3V Devices Symbol Parameter I DD1 Operating I Current DD2 I DD3 Stand-by Current (TTL), 128Mb, 256Mb, 512Mb devices I DD4 Stand-by Current (TTL) 512Mb and 1Gb Dual Die devices Stand-By Current (CMOS) 128Mb, 256Mb, 512Mb ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 20. AC Characteristics for Command, Address, Data Input Alt. Symbol Symbol t Address Latch Low to Write Enable Low ALLWL t ALS t Address Latch High to Write Enable Low ALHWL t Command Latch High ...
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Table 21. AC Characteristics for Operations Alt. Symbol Symbol t ALLRL1 Address Latch Low Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 Ready/Busy Low Ready/Busy ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 25. Command Latch AC Waveforms CL tCLHWL (CL Setup time) tELWL (E Setup time tALLWL (ALSetup time) AL I/O Figure 26. Address Latch AC Waveforms CL tELWL (E Setup time) E tWLWH W ...
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Figure 27. Data Input Latch AC Waveforms CL E tALLWL (ALSetup time) AL tWLWH W (Data Setup time) I/O Figure 28. Sequential Data Output after Read AC Waveforms E R tRLQV (R Accesstime) I/O tBHRL RB Note ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 29. Read Status Register AC Waveform CL tCLHWL E tELWL W R (Data Setup time) I/O Figure 30. Read Electronic Signature AC Waveform I/O 90h Read Electronic Signature Command Note: ...
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Figure 31. Page Read A/ Read B Operation AC Waveform CL E tWLWL 00h or Add.N I/O 01h cycle 1 Command Code Note: Address cycle 4 is only required for 512Mb and 1Gb devices. NAND128-A, NAND256-A, ...
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... Figure 32. Read C Operation, One Page AC Waveform Add. M I/O 50h cycle 1 RB Command Code Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are ‘don’t care’. 42/56 tWHALL Add. M Add. M Add. M cycle 2 cycle 3 cycle 4 Address M Input Busy tWHBH tALLRL2 ...
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Figure 33. Page Program AC Waveform CL E tWLWL (Write Cycle time Add.N I/O 80h cycle 1 RB Page Program Setup Code Note: Address cycle 4 is only required for 512Mb and 1Gb devices. NAND128-A, NAND256-A, NAND512-A, ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 34. Block Erase AC Waveform CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Setup Command Note: Address cycle 3 is required for 512Mb and 1Gb devices ...
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Ready/Busy Signal Electrical Characteristics Figures 37, 36 and 38 show the electrical charac- teristics for the Ready/Busy signal. The value re- quired for the resistor R can be calculated using P the following equation: – V DDmax V OLmax R ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A PACKAGE MECHANICAL Figure 39. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, Package Outline DIE Note: Drawing is not to scale. Table 22. TSOP48 - 48 lead Plastic Thin Small ...
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Figure 40. WSOP48 – 48 lead Plastic Very Very Thin Small Outline 17mm, Package Outline DIE Note: Drawing not to scale. Table 23. WSOP48 lead Plastic Very Very Thin Small Outline ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 41. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline FE Note: Drawing is not to scale Table 24. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package ...
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Figure 42. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline SE FE Note: Drawing is not to scale Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 43. VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline E E2 Note: Drawing is not to scale. Table 26. VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, ...
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Figure 44. TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline FD1 BALL "A1" Note: Drawing is not to scale Table 27. TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, ...
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... E = Lead Free Package, Standard Packing F = Lead Free Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’. For further information on any aspect of this device, please contact your nearest ST Sales Office. ...
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... The structure uses the microcontroller DMA (Direct Memory Access) en- gines to optimize the transfer between the NAND Flash and the system RAM. ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 46. Connection to Microcontroller, With Glue Logic G W CSn A3 Microcontroller Figure 47. Building Storage Modules NAND Flash NAND Flash W Device 54/56 ...
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RELATED DOCUMENTATION STMicroelectronics has published a set of application notes to support the NAND Flash memories. They are available from the ST Website www.st.com . or from your local ST Distributor. REVISION HISTORY Table 29. Document Revision History Date Version ...
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may ...