M27C256B-15F1 STMicroelectronics, M27C256B-15F1 Datasheet - Page 23

• Manufacturer Part Number: M27C256B-15F1
• Description: IC EPROM 256KBIT 150NS 28CDIP
• Manufacturer: STMicroelectronics

Specifications of M27C256B-15F1

• Format - Memory: EPROMs
• Memory Type: UV EPROM
• Memory Size: 256K (32K x 8)
• Speed: 150ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-CDIP (0.600", 15.24mm) Window
• Capacitance, Input: 6 pF
• Capacitance, Output: 12 pF
• Current, Input, Leakage: ±10 μA (Read)
• Current, Operating: 30 mA (Read)
• Current, Output, Leakage: ±10 μA (Read)
• Current, Supply: 30 mA
• Density: 256K
• Organization: 32K×8
• Package Type: FDIP28W
• Temperature, Operating: 0 to +70 °C
• Temperature, Operating, Maximum: 70 °C
• Temperature, Operating, Minimum: 0 °C
• Time, Access: 150 ns
• Time, Fall: ≤20 ns
• Time, Programmable: 100 μA
• Time, Rise: ≤20 ns
• Voltage, Input, High: 6 V (Read)
• Voltage, Input, High Level: 2 V (Min.)
• Voltage, Input, Low: 0.8 V (Read)
• Voltage, Input, Low Level: 0.8 V (Typ.)
• Voltage, Output, High: 4.3 V (Read)
• Voltage, Output, Low: 0.4 V (Read)
• Voltage, Programmable: 12.75 V ± 0.25 V
• Voltage, Supply: 5 V
• Memory Configuration: 32K X 8
• Access Time: 150ns
• Supply Voltage Range: 4.5V To 5V
• Memory Case Style: DIP
• No. Of Pins: 28
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1650-5

M27C256B
7
Revision history
Table 16.
July 1998
20-Sep-2000
29-Nov-2000
02-Apr-2001
29-Aug-2002
18-May-2006
Date
Document revision history
Version
1.0
1.1
1.2
1.3
1.4
2
First Issue
AN620 Reference removed
PLCC codification changed
FDIP28W mechanical dimensions changed
Package mechanical data clarified for PDIP28
PLCC32
Document converted to new template (sections added, information
moved).
TSOP28 package removed. Packages are ECOPACK® compliant. X
option removed from
(Table
14.,
Figure
Table 15: Ordering information
11.) and TSOP28
(Table
Revision Details
15.)
(Table
(Table
(Table
12.)
15.,
scheme.
13.),
Revision history
Figure
13.)
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