M58LT256JST8ZA6E NUMONYX, M58LT256JST8ZA6E Datasheet
M58LT256JST8ZA6E
Specifications of M58LT256JST8ZA6E
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M58LT256JST8ZA6E Summary of contents
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... December 2007 1.8 V supply, secure Flash memories ■ Electronic signature – Manufacturer code: 20h – Top device codes: M58LT256JST: 885Eh – Bottom device codes M58LT256JSB: 885Fh ■ TBGA64 package – ECOPACK® compliant = Rev 4 M58LT256JST M58LT256JSB BGA TBGA64 (ZA 1/108 www.numonyx.com 1 ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M58LT256JST, M58LT256JSB 4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 6.9 Burst length bits (CR2-CR0 ...
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M58LT256JST, M58LT256JSB List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 48. Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 105 Table ...
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... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2. TBGA64 package connections (top view through package Figure 3. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 5. X latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 6. Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 7. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 8. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 9 ...
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... It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in The parameter blocks are located at the top of the memory address space for the M58LT256JST, and at the bottom for the M58LT256JSB. Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed ...
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... Protection Register and the other for the 16 OTP (one-time-programmable) Protection Registers of 128 bits each. The first Protection Register is divided into two segments bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. ...
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Description Table 1. Signal names Signal name A0-A23 DQ0-DQ15 WAIT DDQ SSQ NC DU 10/108 Function Address inputs Data input/outputs, command inputs Chip Enable Output Enable ...
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M58LT256JST, M58LT256JSB Figure 2. TBGA64 package connections (top view through package DQ8 F K A22 A12 ...
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... Description Table 2. Bank architecture Number Parameter bank Bank 1 Bank 2 Bank 3 Bank 14 Bank 15 Figure 3. Memory map M58LT256JST - Top Boot Block 000000h 00FFFFh Bank 15 0F0000h 0FFFFFh C00000h C0FFFFh Bank 3 CF0000h CFFFFFh D00000h D0FFFFh Bank 2 DF0000h DFFFFFh E00000h E0FFFFh Bank 1 EF0000h EFFFFFh F00000h F0FFFFh ...
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... Figure 1: Logic diagram connected to this device. 2.1 Address inputs (A0-A23) The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the Program/Erase Controller. 2.2 Data input/output (DQ0-DQ15) The data I/O output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation ...
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... Reset one clock cycle in advance. 2.10 V supply voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (read, program and erase). 2.11 V supply voltage DDQ V provides the power supply to the I/O pins and enables all outputs to be powered ...
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M58LT256JST, M58LT256JSB 2.13 V ground SS V ground is the reference for the core supply. It must be connected to the system ground. SS 2.14 V ground SSQ V ground is the reference for the input/output circuitry driven by V ...
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... Bus write Bus write operations write commands to the memory or latch input data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at V Enable Commands, input data and addresses are latched on the rising edge of Write IH Enable or Chip Enable, whichever occurs first ...
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... Standby Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at V consumption is reduced to the standby level I independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V during a program or erase operation, the device enters standby mode when finished ...
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... Command interface 4 Command interface All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. An internal Program/Erase Controller manages all timings and verifies the correct execution of the program and erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation ...
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... The Read Array command returns the addressed bank to read array mode. One bus write cycle is required to issue the Read Array command. Once a bank is in read array mode, subsequent read operations output the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank ...
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... Dual operations between the parameter bank and the CFI memory space are not allowed (see for details). See Appendix B: Common Flash for details on the information contained in the common Flash interface memory area. 20/108 M58LT256JST, M58LT256JSB for details). Table 15: Dual operation limitations ...
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M58LT256JST, M58LT256JSB 4.5 Clear Status Register command The Clear Status Register command resets (set to ‘0’) all error bits (SR1 and 5) in the Status Register. One bus write cycle is required to issue the Clear Status Register ...
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Command interface 4.7 The Blank Check command The Blank Check command checks whether a main array block has been completely erased. Only one block at a time can be checked. To use the Blank Check command V must be equal ...
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... M58LT256JST, M58LT256JSB 4.8 Program command The program command is used to program a single word to the memory array. If the block being programmed is protected, then the program operation aborts, the data in the block is not changed, and the Status Register outputs the error. Two bus write cycles are required to issue the Program command. ...
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... Clear the Status Register before re-issuing the command. If the block being programmed is protected, an error is set in the Status Register and the operation aborts without affecting the data in the memory array. During buffer program operations the bank being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands, and all other commands are ignored ...
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M58LT256JST, M58LT256JSB 4.10 Buffer Enhanced Factory Program command The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical used to program one or more write ...
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... Status Register bit SR0 should be read between each bus write cycle to check that the P/EC is ready for the next word. 3. Once the write buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary. ...
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M58LT256JST, M58LT256JSB 4.11 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a program or block erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One ...
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... Register results in a Status Register error. The Protection Register program cannot be suspended. Dual operations between the parameter bank and the Protection Register memory space are not allowed (see Dual operation limitations The two Protection Register Locks protect the OTP segments from further modification. The protection of the OTP segments is not reversible ...
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M58LT256JST, M58LT256JSB 4.14 Set Configuration Register command The Set Configuration Register command writes a new value to the Configuration Register. Two bus write cycles are required to issue the Set Configuration Register command. ● The first cycle sets up the ...
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Command interface Table 5. Standard commands Commands Read Array Read Status Register Read Electronic Signature Read CFI query Clear Status Register Block Erase Program (4) Buffer Program Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Protect Block ...
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... BKA or 2 80h WA ( ≥ ( NOT Not Block Address Code Top Bottom Protected Unprotected Numonyx factory default OTP area permanently protected Command interface (1) Bus write operations 3rd Final -1 Add Data CBh D0h Address (h) Data (h) Bank address + 000 0020 Bank address + 001 ...
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... Command interface Figure 4. Protection Register memory map Protection Register Lock 32/108 PROTECTION REGISTERS 109h PR16 User Programmable OTP 102h 91h PR1 User Programmable OTP 8Ah 89h 88h 88h PR0 User Programmable OTP 85h 84h Unique device number 81h Protection Register Lock ...
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M58LT256JST, M58LT256JSB Table 8. Protection Register locks Lock Number Address Lock 1 80h Lock 2 89h Bits Pre-programmed to protect Unique Device Number, address Bit 0 81h to 84h in PR0 Bit 1 Protects 64 bits of OTP segment, address ...
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... The erase suspend status bit indicates that an erase operation has been suspended in the addressed block. When the erase suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The erase suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive) ...
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... PP , the memory is protected and program and erase operations cannot PPLK status bit must be set Low by a Clear Status Register command ...
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... The bank write status bit indicates whether the addressed bank is programming or erasing. In buffer enhanced factory program mode the multiple word program bit shows if the device is ready to accept a new word to be programmed to the memory array. The bank write status bit should only be considered valid when the Program/Erase Controller status bit SR7 is Low (set to ‘ ...
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M58LT256JST, M58LT256JSB Table 9. Status Register bits Bit Name SR7 P/EC status SR6 Erase suspend status Status Erase/blank check SR5 status SR4 Program status SR3 V status PP Program suspend SR2 status Block protection SR1 status Bank write status SR0 ...
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... For correct operation the X latency bits can only assume the values in Configuration Register. Table 10 shows how to set the X latency parameter, taking into account the speed class of the device and the frequency used to read the Flash memory in synchronous mode. Table 10. X latency settings fmax 30 MHz ...
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... Burst type bit (CR7) The burst type bit determines the sequence of addresses read during synchronous burst reads. The burst type bit is High (set to ’1’), as the memory outputs from sequential addresses only. See Table 12: Burst type definition starting address in sequential mode. ...
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Configuration Register 6.7 Valid clock edge bit (CR6) The valid clock edge bit, CR6, configures the active edge of the Clock, K, during synchronous read operations. When the valid clock edge bit is Low (set to ’0’) the falling edge ...
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M58LT256JST, M58LT256JSB Table 11. Configuration Register Bit CR15 Read select CR14 Reserved CR13-CR11 X latency CR10 Wait polarity CR9 Data output configuration CR8 Wait configuration CR7 Burst type CR6 Valid clock edge CR5-CR4 Reserved CR3 Wrap burst CR2-CR0 Burst length ...
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Configuration Register Table 12. Burst type definition Start add. 4 words 0 0-1-2-3 0-1-2-3-4-5-6-7 1 1-2-3-0 1-2-3-4-5-6-7-0 2 2-3-0-1 2-3-4-5-6-7-0-1 3 3-0-1-2 3-4-5-6-7-0-1-2 ... 7 7-4-5-6 7-0-1-2-3-4-5-6 ... 12-13-14-15-8-9- 12 12-13-14-15 13-14-15-8-9-10- 13 13-14-15-12 14-15-8-9-10-11- 14 14-15-12-13 15-8-9-10-11-12- 15 15-12-13-14 ...
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M58LT256JST, M58LT256JSB Figure 5. X latency and data output configuration example 1st cycle A23-A0 VALID ADDRESS tDELAY tAVK_CPU DQ15-DQ0 1. The settings shown are X latency = 4, data output held for one clock cycle. Figure 6. ...
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... Asynchronous read mode In asynchronous read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, common Flash interface or the electronic signature, depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for asynchronous operations. ...
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... In synchronous burst read mode the data is output in bursts synchronized with the clock possible to perform burst reads across bank boundaries. Synchronous burst read mode can only be used to read the memory array. For other read operations, such as read Status Register, read CFI and read electronic signature, single synchronous read or asynchronous random access read must be used ...
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... Single synchronous read mode Single synchronous read operations are similar to synchronous burst read operations, except that the memory outputs the same data to the end of the operation. Synchronous single reads are used to read the electronic signature, Status Register, CFI, block protection status, Configuration Register status or Protection Register. When the addressed bank is in read CFI, read Status Register or read electronic signature mode, the WAIT signal is asserted during the X latency and at the end and 16-word burst ...
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... Dual operations and multiple bank architecture The multiple bank architecture of the M58LT256JST/B gives greater flexibility for software developers to split the code and data spaces within the memory array. The dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased ...
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Dual operations and multiple bank architecture Table 13. Dual operations allowed in other banks Status of bank Idle Programming Erasing Program suspended Erase suspended Table 14. Dual operations allowed in same bank Status of bank Read Array Idle Programming Erasing ...
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M58LT256JST, M58LT256JSB Table 15. Dual operation limitations Current status Programming/erasing parameter blocks Programming/ erasing main Not located in blocks Programming OTP Dual operations and multiple bank architecture Read CFI/OTP / electronic signature No Located in parameter Yes bank parameter Yes ...
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Block protection 9 Block protection The M58LT256JST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency. This protection scheme has two levels of protection. ● Protect/unprotect - this first level ...
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M58LT256JST, M58LT256JSB 9.4 Protection operations during erase suspend Changes to block protection status can be performed during an erase suspend by using the standard protection command sequences to unprotect or protect a block. This is useful in the case when ...
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... Table 16. Exact erase times may change depending on the memory array condition. The best case is when all the bits in the block are at ‘0’ (pre-programmed). The worst case is when all the bits in the block are at ‘1’ (not pre-programmed). Usually, the system overhead is negligible with respect to the erase time ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 17. ...
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DC and AC parameters 12 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests ...
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M58LT256JST, M58LT256JSB Figure 8. AC measurement load circuit Table 19. Capacitance Symbol C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. V DDQ V DD DEVICE UNDER TEST 0.1µF 0.1µ includes JIG capacitance ...
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DC and AC parameters Table 20. DC characteristics - currents Symbol I Input leakage current LI I Output leakage current LO Supply current asynchronous Read (f=5 MHz) I DD1 Supply current synchronous read (f=52 MHz) I Supply current (reset) DD2 ...
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M58LT256JST, M58LT256JSB Table 21. DC characteristics - voltages Symbol Parameter V Input Low voltage IL V Input High voltage IH V Output Low voltage OL V Output High voltage program voltage-logic PP1 program voltage ...
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DC and AC parameters Figure 9. Asynchronous random access read AC waveforms 58/108 M58LT256JST, M58LT256JSB ...
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M58LT256JST, M58LT256JSB Figure 10. Asynchronous page read AC waveforms DC and AC parameters 59/108 ...
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DC and AC parameters Table 22. Asynchronous read AC characteristics Symbol Alt t t AVAV t t AVQV ACC t t AVQV1 PAGE ( AXQX t ELTV ( ELQV (1) t ELQX t EHTZ (1) t ...
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M58LT256JST, M58LT256JSB Figure 11. Synchronous burst read AC waveforms DC and AC parameters 61/108 ...
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DC and AC parameters Figure 12. Single synchronous read AC waveforms A0-A23 L ( Hi-Z DQ0-DQ15 Hi-Z (1,2) WAIT 1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 2. ...
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M58LT256JST, M58LT256JSB Figure 13. Synchronous burst read suspend AC waveforms DC and AC parameters 63/108 ...
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DC and AC parameters Figure 14. Clock input AC waveform Table 23. Synchronous read AC characteristics Symbol t AVKH t ELKH t EHEL t EHTZ t KHAX t KHQV t KHTV t KHQX t KHTX t t LLKH ADVLCLKH t ...
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M58LT256JST, M58LT256JSB Figure 15. Write AC waveforms, Write Enable controlled DC and AC parameters 65/108 ...
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DC and AC parameters Table 24. Write AC characteristics, Write Enable controlled Symbol Alt t t AVAV WC t AVLH (3) t AVWH t t DVWH DS t ELLH t t ELWL CS t ELQV t ELKV t GHWL t ...
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M58LT256JST, M58LT256JSB Figure 16. Write AC waveforms, Chip Enable controlled DC and AC parameters 67/108 ...
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DC and AC parameters Table 25. Write AC characteristics, Chip Enable controlled Symbol t AVAV t AVEH t AVLH t DVEH t EHAX t EHDX t EHEL t EHGL t EHWH t ELKV t ELEH t ELLH t ELQV t ...
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M58LT256JST, M58LT256JSB Figure 17. Reset and power-up AC waveforms tVDHPH VDD, VDDQ Table 26. Reset and power-up AC characteristics Symbol Parameter Reset Low to t PLWL Write Enable Low, t PLEL Chip Enable Low, t ...
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... Package mechanical 13 Package mechanical To meet environmental requirements, Numonyx offers these devices in ECOPACK® packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ...
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M58LT256JST, M58LT256JSB Table 27. TBGA64 10 × active ball array pitch, package mechanical data Symbol 10.000 D1 ddd e E 13.000 Millimeters ...
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... Blank = standard packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx sales office nearest to you. 72/108 M58LT256JST = 2 ...
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M58LT256JST, M58LT256JSB Appendix A Block address tables The following set of equations can be used to calculate a complete set of block addresses using the information contained in Tables To calculate the block base address from the block number: First ...
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Block address tables Table 29. M58LT256JST - parameter bank block addresses Block number 74/108 Size (KWords ...
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M58LT256JST, M58LT256JSB Table 30. M58LT256JST - main bank base addresses Bank number There are two bank regions: bank region 1 contains all the banks ...
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Block address tables Table 32. M58LT256JSB - parameter bank block addresses Block number 76/108 Size (KWords ...
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M58LT256JST, M58LT256JSB Table 33. M58LT256JSB - main bank base addresses Bank number There are two bank regions: bank region 2 contains all the banks ...
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... The CFI data structure also contains a security area where a 64-bit unique security number is written (see Figure 4: Protection Register memory in read mode by the final user impossible to change the security number after it has been written by Numonyx. Issue a Read Array command to return to read mode. Table 35. Query structure overview Offset ...
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... Table 39) 0001h 0000h Alternate vendor command set and control interface ID code second vendor - specified algorithm supported 0000h Address for alternate algorithm extended query table 0000h Common Flash interface Description M58LT256JST M58LT256JSB Value Numonyx Top Bottom "Q" "R" "Y" 10Ah NA NA 79/108 ...
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Common Flash interface Table 37. CFI query system interface information Offset Data 01Bh 0017h 01Ch 0020h 01Dh 0085h 01Eh 0095h 01Fh 0008h 020h 0009h 021h 000Ah 022h 0000h 023h 0001h 024h 0001h 025h 0002h 026h 0000h 80/108 Description V logic ...
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M58LT256JST, M58LT256JSB Table 38. Device geometry definition Offset Data 027h 0019h 028h 0001h 029h 0000h 02Ah 0006h 02Bh 0000h 02Ch 0002h 02Dh 00FEh 02Eh 0000h 02Fh 0000h 030h 0002h 031h 0003h 032h 0000h 033h 0080h 034h 0000h 035h Reserved Reserved ...
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Common Flash interface Table 39. Primary algorithm-specific extended query table Offset (P)h = 10Ah 0050h 0052h 0049h (P+3)h =10Dh 0031h Major version number, ASCII (P+4)h = 10Eh 0033h Minor version number, ASCII (P+5)h = 10Fh 00E6h Extended query table contents ...
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M58LT256JST, M58LT256JSB Table 40. Protection register information Offset (P+E)h = 118h (P+F)h = 119h (P+10)h = 11Ah (P+ 11)h = 11Bh (P+12)h = 11Ch (P+13)h = 11Dh (P+14)h = 11Eh (P+15)h = 11Fh (P+16)h = 120h (P+17)h = 121h (P+18)h ...
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Common Flash interface Table 41. Burst read information Offset (P+1D)h = 127h (P+1E)h = 128h (P+1F)h = 129h (P+20)h = 12Ah (P-21)h = 12Bh (P+22)h = 12Ch 84/108 Data Description Page-mode read capability n bits 0-7 n’ such that 2 ...
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M58LT256JST, M58LT256JSB Table 42. Bank and erase block region information M58LT256JST Offset (P+23)h = 12Dh 1. The variable pointer which is defined at CFI offset 015h. 2. Bank regions. There are two bank regions, see Tables Table ...
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Common Flash interface Table 43. Bank and erase block region 1 information (continued) M58LT256JST Offset Data (P+30)h = 13Ah 02h (P+31)h = 13Bh 03h 1. The variable pointer which is defined at CFI offset 015h. 2. Bank ...
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M58LT256JST, M58LT256JSB Table 44. Bank and erase block region 2 information M58LT256JST Offset Data (P+32)h = 13Ch 01h (P+33)h = 13Dh 00h (P+34)h = 13Eh 11h (P+35)h = 13Fh 00h (P+36)h = 140h 00h (P+37)h = 141h 02h (P+38)h = ...
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Common Flash interface Table 44. Bank and erase block region 2 information (continued) M58LT256JST Offset Data (P+40)h = 14Ah 03h (P+41)h = 14Bh 00h (P+42)h = 14Ch 80h (P+43)h = 14Dh 00h (P+44)h = 14Eh 64h (P+45)h = 14Fh 00h ...
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... If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 ...
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... Any address within the bank can equally be used error is found, the Status Register must be cleared before further Program/Erase operations. 90/108 blank_check_command (blockToCheck) { writeToFlash (blockToCheck, 0xBC); writeToFlash (blockToCheck, 0xCB); /* Memory enters read status state after the Blank Check Command */ (status_register.SR4==1) && (status_register.SR5==1) Command Sequence /* command sequence error */ Error (2) if (status_register ...
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... Routine for Error Check by reading SR3, SR4 and SR1. Buffer_Program_command (Start_Address, n, buffer_Program buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+ {writeToFlash (Start_Address, 0xE8) ; ...
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Flowcharts and pseudocodes Figure 22. Program suspend and resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR2 = 1 YES Write FFh Read data from another address Write D0h (1) ...
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... If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used. erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; writeToFlash (blockToErase, 0xD0 Memory enters read status state after the Erase Command */ do { status_register=readFlash (blockToErase must be toggled*/ } while (status_register.SR7 ...
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Flowcharts and pseudocodes Figure 24. Erase suspend and resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR6 = 1 YES Write FFh Read data from another block or Program or ...
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M58LT256JST, M58LT256JSB Figure 25. Protect/unprotect operation flowchart and pseudocode Start Write 60h (1) Write 01h, D0h Write 90h (1) Read Block Protect State Protection change confirmed? YES Write FFh (1) End 1. Any address within the bank can equally be ...
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... If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 96/108 protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 ...
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M58LT256JST, M58LT256JSB Figure 27. Buffer enhanced factory program flowchart and pseudocode Address WA1 Address WA1 Read Status NO NO Initialize count SR4 = 1 Read Status Register Address WA1 SR3 and SR1for errors Increment Count Exit Write ...
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Command interface state tables Appendix D Command interface state tables Table 45. Command interface states - modify table, next state Current CI State Program Read Program (3)(4) (2) Setup Array (FFh) (10/40h) Program Ready Ready Setup Protect/CR Setup Ready (Protect ...
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M58LT256JST, M58LT256JSB Table 45. Command interface states - modify table, next state Current CI State Program Read Program (3)(4) (2) Setup Array (FFh) (10/40h) Setup IS in Erase Busy Erase Busy Busy IS in Erase Erase Busy Erase Program Suspend ...
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Command interface state tables Table 45. Command interface states - modify table, next state Current CI State Program Read Program (3)(4) (2) Setup Array (FFh) (10/40h) Setup Blank Check Busy Protect/CR Setup Erase Suspend (Protect Error) in Erase Suspend Setup ...
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M58LT256JST, M58LT256JSB Table 46. Command Interface states - modify table, next output state Read Program Current CI State (4) Array Setup Program (3) (5) (FFh) (10/40h) Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP ...
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Command interface state tables Table 46. Command Interface states - modify table, next output state Read Program Current CI State (4) Array Setup Program (3) (5) (FFh) (10/40h) OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend ...
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M58LT256JST, M58LT256JSB Table 47. Command interface states - lock table, next state Current CI State Protect/CR Setup (60h) Ready Protect/CR Setup Protect/CR Setup Ready (Protect error) Setup OTP Busy IS in OTP Busy IS in OTP busy Setup Busy IS ...
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Command interface state tables Table 47. Command interface states - lock table, next state Current CI State Protect/CR Setup (60h) Setup Busy IS in Program busy in ES Program IS in Program in Erase busy in ES Suspend Suspend IS ...
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M58LT256JST, M58LT256JSB Table 48. Command interface states - lock table, next output state Current CI State Protect/CR Setup Program Setup Erase Setup OTP Setup Program in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer ...
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Command interface state tables Table 48. Command interface states - lock table, next output state (continued) Current CI State Protect/CR Setup OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase ...
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... Small text changes. Changed deassertion condition in read mode to state that WAIT is only de-asserted when output data 3 is valid. Changed T A Absolute maximum ratings 4 Applied Numonyx branding. Revision history Changes Table 11: and Note 2 added. modified. Table 17: Absolute maximum currents. voltages. modified. ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...