CY7C1512AV18-200BZXI Cypress Semiconductor Corp, CY7C1512AV18-200BZXI Datasheet
CY7C1512AV18-200BZXI
Specifications of CY7C1512AV18-200BZXI
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CY7C1512AV18-200BZXI Summary of contents
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... To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 8-bit words (CY7C1510AV18), 9-bit words (CY7C1525AV18), 18-bit words (CY7C1512AV18), or 36-bit words (CY7C1514AV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the ...
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... D [8:0] 22 Address A (21:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [0] Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Write Write Address Reg Reg Register Control Logic Read Data Reg Reg. Reg. 8 Reg. Write Write Address Reg Reg Register Control Logic Read Data Reg ...
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... Logic Block Diagram (CY7C1512AV18 [17:0] 21 Address A (20:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram (CY7C1514AV18 [35:0] 20 Address A (19:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 ...
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... Pin Configuration The pin configuration for CY7C1510AV18, CY7C1525AV18, CY7C1512AV18, and CY7C1514AV18 follow DOFF V V REF DDQ TDO TCK DOFF V V REF DDQ TDO TCK A Note 1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. Document #: 001-06984 Rev. *C ...
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... Pin Configuration (continued) The pin configuration for CY7C1510AV18, CY7C1525AV18, CY7C1512AV18, and CY7C1514AV18 follow NC/144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO TCK ...
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... These address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each for CY7C1510AV18 arrays each for CY7C1525AV18 arrays each 18) for CY7C1512AV18, and arrays each 36) for CY7C1514AV18. Therefore, only 22 address inputs are needed to access the entire memory array of CY7C1510AV18 and CY7C1525AV18, 21 address inputs for CY7C1512AV18, and 20 address inputs for CY7C1514AV18 ...
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... Ground Ground for the device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Pin Description Switching Characteristics on page 23. Switching Characteristics on page 23. output impedance are set to 0.2 x RQ, where resistor connected [x:0] ...
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... This includes forwarding data from a write cycle that was initiated on the previous K clock rise. Depth Expansion The CY7C1512AV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled using on the rising edge of the positive input clock only (K). Each port [17:0] select input can deselect the specified port ...
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... Delayed 50ohms Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 DLL These chips use a DLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum ...
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... Truth Table The truth table for CY7C1510AV18, CY7C1525AV18, CY7C1512AV18, and CY7C1514AV18 follow. Operation Write Cycle: Load address on the rising edge of K; input write data on K and K rising edges. Read Cycle: Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges. ...
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... L– – Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 [ Comments – During the Data portion of a write sequence, all four bytes (D the device. L–H During the Data portion of a write sequence, all four bytes (D the device. – During the Data portion of a write sequence, only the lower byte (D into the device ...
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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 15 ...
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... Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins ...
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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1-DR ...
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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 11. Overshoot: V (AC) < 0.85V (Pulse width less than t IH DDQ 12. All Voltage referenced to Ground. Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 0 Bypass Register Instruction Register ...
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... CS CH 14. Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Description [14] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50Ω ...
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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Value CY7C1525AV18 CY7C1512AV18 001 001 11010011010001100 11010011010010100 11010011010100100 Defines the type of ...
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... Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D 11B ...
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... DDQ DOFF Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as t ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior ...
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... RQ <= 350 ohms. OL DDQ 18. V (min) = 0.68V or 0.46V , whichever is larger, V REF DDQ Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch-up Current ................................................... > 200 mA Operating Range DD Range + 0.5V DDQ Commercial + 0 ...
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... Tested initially and after any design or process change that may affect these parameters. Parameter Description Θ Thermal Resistance JA (Junction to Ambient) Θ Thermal Resistance JC (Junction to Case) Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Test Conditions Max V , 250MHz (x8) DD Both Ports Deselected, (x9) ≥ V ≤ ...
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... Note 19. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V 250Ω, V pulse levels of 0.25V to 1.25V, and output loading of the specified I Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 V = 0.75V REF V 0.75V R = 50Ω ...
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... These parameters are only guaranteed by design and are not tested in production. KHKH 24 are specified with a load capacitance part (b) of CHZ CLZ 25. At any voltage and temperature t is less than t CHZ Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Description [21] , BWS ) BWS ) 2 3 [23] ...
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... Outputs are disabled (High-Z) one clock cycle after a NOP. 28. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 WRITE WRITE READ ...
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... CY7C1510AV18-200BZXC CY7C1525AV18-200BZXC CY7C1512AV18-200BZXC CY7C1514AV18-200BZXC CY7C1510AV18-200BZI CY7C1525AV18-200BZI CY7C1512AV18-200BZI CY7C1514AV18-200BZI CY7C1510AV18-200BZXI CY7C1525AV18-200BZXI CY7C1512AV18-200BZXI CY7C1514AV18-200BZXI Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...
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... CY7C1510AV18-167BZXI CY7C1525AV18-167BZXI CY7C1512AV18-167BZXI CY7C1514AV18-167BZXI Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...
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... PIN 1 CORNER SEATING PLANE C Document #: 001-06984 Rev. *C CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 0.15(4X) NOTES : SOLDER PAD TYPE : NON SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.65g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AD BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. +0.14 Ø0.50 (165X) -0. ...
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... Document History Page Document Title: CY7C1510AV18/CY7C1525AV18/CY7C1512AV18/CY7C1514AV18, 72-Mbit QDR™-II SRAM 2-Word Burst Architecture Document Number: 001-06984 ISSUE ORIG. OF REV. ECN NO. DATE CHANGE ** 433241 See ECN NXR *A 462002 See ECN NXR *B 503690 See ECN VKN *C 1523363 See ECN VKN/AESA Converted from preliminary to final © ...