DS2505P+T&R Maxim Integrated Products, DS2505P+T&R Datasheet - Page 13

• Manufacturer Part Number: DS2505P+T&R
• Description: IC OTP 16KBIT 6TSOC
• Manufacturer: Maxim Integrated Products

Specifications of DS2505P+T&R

• Format - Memory: EPROMs
• Memory Type: OTP EPROM
• Memory Size: 16K (16K x 1)
• Interface: 1-Wire Serial
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 6-TSOC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Speed: -

DS2505
As the DS2505 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator
that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte and
the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the
DS2505 with sixteen read time slots to confirm that the address incremented properly and the data byte
was received correctly. If the CRC is incorrect, a reset pulse must be issued and the Write Memory
command sequence must be restarted. If the CRC is correct, the bus master will issue a programming
pulse and the selected byte in memory will be programmed.
Note that the initial pass through the Write Memory flow chart will generate a 16-bit CRC value that is
the result of shifting the command byte into the CRC generator, followed by the two address bytes, and
finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS2505
automatically incrementing its address counter will generate a 16-bit CRC that is the result of loading
(not shifting) the new (incremented) address into the CRC generator and then shifting in the new data
byte.
For both of these cases, the decision to continue (to apply a program pulse to the DS2505) is made
entirely by the bus master, since the DS2505 will not be able to determine if the 16-bit CRC calculated by
the bus master agrees with the 16-bit CRC calculated by the DS2505. If an incorrect CRC is ignored and
a program pulse is applied by the bus master, incorrect programming could occur within the DS2505.
Also note that the DS2505 will always increment its internal address counter after the receipt of the eight
read time slots used to confirm the programming of the selected EPROM byte. The decision to continue
is again made entirely by the bus master. Therefore, if the EPROM data byte does not match the supplied
data byte but the master continues with the Write Memory command, incorrect programming could occur
within the DS2505. The Write Memory command sequence can be ended at any point by issuing a reset
pulse.
To save time when writing more than 1 consecutive byte of the DS2505’s data memory it is possible to
omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the
EPROM memory. This saves 16 time slots or 976 µs for every byte to be programmed. This speed-
programming mode is accessed with the command code F3H instead of 0FH. It follows basically the
same flow chart as the Write Memory command, but skips sending the CRC immediately preceding the
program pulse. This command should only be used if the electrical contact between bus master and the
DS2505 is firm, since a poor contact may result in corrupted data inside the EPROM memory.
WRITE STATUS [55H]/SPEED WRITE STATUS [F5]
The Write Status command is used to program the EPROM Status data field. The bus master will follow
the command byte with a 2-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of status data
(D7:D0). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the DS2505
and read back by the bus master to confirm that the correct command word, starting address, and data
byte were received.
If the CRC read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must
be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the
1-Wire bus for 480 µs) is issued by the bus master. Prior to programming, the EPROM Status data field
will appear as logical 1s. For each bit in the data byte provided by the bus master that is set to a logical 0,
the corresponding bit in the selected byte of the EPROM Status data field will be programmed to a logical
0 after the programming pulse has been applied at that byte location.
After the 480 µs programming pulse is applied and the data line returns to the idle level, the bus master
issues eight read time slots to verify that the appropriate bits have been programmed. The DS2505
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