M45PE40-VMP6G NUMONYX, M45PE40-VMP6G Datasheet - Page 8

• Manufacturer Part Number: M45PE40-VMP6G
• Description: IC FLASH 4MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE40-VMP6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Clock Frequency: 25MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: VDFPN
• No. Of Pins: 8
• Base Number: 45
• Frequency: 75MHz
• Ic Generic Number: 45PE40
• Memory Configuration: 512K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal descriptions
2
2.1
2.2
2.3
2.4
2.5
2.6
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Signal descriptions
Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at serial data input (D) are latched on the rising edge of Serial Clock (C). Data on
serial data output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and serial data output (Q) is at high
impedance. Unless an internal read, program, erase or write cycle is in progress, the device
will be in the standby power mode (this is not the deep power-down mode). Driving Chip
Select (S) Low selects the device, placing it in the active power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
Reset (Reset)
The Reset (Reset) input provides a hardware reset for the memory. In this mode, the outputs
are high impedance.
When Reset (Reset) is driven High, the memory is in the normal operating mode. When
Reset (Reset) is driven Low, the memory will enter the reset mode, provided that no internal
operation is currently in progress. Driving Reset (Reset) Low while an internal operation is in
progress has no effect on that internal operation (a write cycle, program cycle, or erase
cycle).
Write Protect (W)
This input signal puts the device in the hardware protected mode, when Write Protect (W) is
connected to V
them from write, program and erase operations. When Write Protect (W) is connected to
V
CC
, the first 256 pages of memory behave like the other pages of memory.
SS
, causing the first 256 pages of memory to become read-only by protecting
M45PE40