M45PE40-VMP6TG NUMONYX, M45PE40-VMP6TG Datasheet
M45PE40-VMP6TG
Specifications of M45PE40-VMP6TG
M45PE40-VMP6TGTR
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M45PE40-VMP6TG Summary of contents
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... Deep power-down mode 1 µA (typical) More than 100 000 write cycles More than 20 years data retention Packages – ECOPACK® (RoHS compliant) May 2008 4-Mbit, page-erasable serial flash memory Rev 9 M45PE40 VFQFPN8 (MP) 6 × (MLP8) SO8W (MW) 208 mils width SO8N (MN) 150 mils width 1/49 www ...
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... Active power, standby power and deep power-down modes . . . . . . . . . . 13 4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Write Enable (WREN 6.2 Write disable (WRDI 6.3 Read identification (RDID 6.4 Read status register (RDSR 6.4.1 2/49 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 M45PE40 ...
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... M45PE40 6.4.2 6.5 Read data bytes (READ 6.6 Read data bytes at higher speed (FAST_READ 6.7 Page write (PW 6.8 Page program (PP 6.9 Page erase (PE 6.10 Sector erase (SE 6.11 Deep power-down (DP 6.12 Release from deep power-down (RDP Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 Maximum ratings ...
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... Table 18. SO8 wide – 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 19. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4/49 M45PE40 ...
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... M45PE40 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8. Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 20 Figure 9 ...
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... Description 1 Description The M45PE40 is a 4-Mbit (512 Kbit x8 bit) serial paged flash memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle ...
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... There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Section 11: Package mechanical Function Serial Clock Serial data input Serial data output Chip Select Write Protect Reset Supply voltage Ground M45PE40 Reset ...
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... This input signal puts the device in the hardware protected mode, when Write Protect (W) is connected them from write, program and erase operations. When Write Protect (W) is connected the first 256 pages of memory behave like the other pages of memory. CC 8/49 , causing the first 256 pages of memory to become read-only by protecting M45PE40 ...
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... M45PE40 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC Signal descriptions 9/49 ...
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... Resistors R (represented in that the M45PE40 is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all inputs/outputs are in high impedance at ...
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... M45PE40 Example pF, that is R*C p master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA µs <=> the application must ensure that the bus p MSB SPI modes MSB AI01438B 11/49 ...
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... Table 14: AC characteristics (50 MHz operation, T9HX (0.11 µm) 12/49 Section 6.7: Page write operation), and Table 15: AC characteristics (75 MHz process)). M45PE40 (PW), ...
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... M45PE40 4.3 A fast way to modify data The page program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to ‘0’ that had previously been set to ‘1’. This might be: when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier page erase (PE) or sector erase (SE) instruction ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M45PE40 features the following data protection mechanisms: Power on reset and an internal timer (t changes while the power supply is outside the operating specification ...
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... M45PE40 5 Memory organization The memory is organized as: 2048 pages (256 bytes each) 524288 bytes (8 bits each) 8 sectors (512 Kbits, 65536 bytes each). Each page can be individually: programmed (bits are programmed from erased (bits are erased from written (bits are changed to either The device is page or sector erasable (bits are erased from 0 to 1). ...
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... Memory organization Figure 5. Block diagram Reset W Control logic Address register and counter 16/49 High voltage generator I/O shift register 256-byte data buffer 10000h 00000h 256 bytes (page size) X decoder M45PE40 Status register 7FFFFh First 256 pages can be made read-only 000FFh AI04042B ...
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... M45PE40 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (D), each bit being latched on the rising edges of Serial Clock (C) ...
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... Page program (PP) instruction completion Page erase (PE) instruction completion Sector erase (SE) instruction completion Figure 7. Write disable (WRDI) instruction sequence 18/49 (Figure 6) sets the write enable latch (WEL) bit Instruction High Impedance AI02281E (Figure 7) resets the write enable latch (WEL) bit Instruction High Impedance AI03750D M45PE40 ...
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... M45PE40 6.3 Read identification (RDID) The read identification (RDID) instruction allows to read the device identification data: Manufacturer identification (1 byte) Device identification (2 bytes) A unique ID code (UID) (17 bytes, of which 16 available upon customer request) The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. ...
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... Instructions Figure 8. Read identification (RDID) instruction sequence and data-out sequence 1. The unique ID code is available only in the T9HX process (see 20/49 Important note on page 6). M45PE40 ...
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... M45PE40 6.4 Read status register (RDSR) The read status register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase or write cycle is in progress. When one of these cycles is in progress recommended to check the write in progress (WIP) bit before sending a new instruction to the device ...
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... Figure 10. Read data bytes (READ) instruction sequence and data-out sequence High Impedance Q 1. Address bits A23 to A19 are don’t care. 22/49 Figure 10 Instruction 24-bit address MSB Data out MSB M45PE40 Data out 2 7 AI03748D ...
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... M45PE40 6.6 Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...
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... A page write (PW) instruction applied to a page that is hardware protected is not executed. Any page write (PW) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 24/49 Figure 12. Table 14: AC characteristics (50 MHz M45PE40 process)). ...
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... M45PE40 Figure 12. Page write (PW) instruction sequence Address bits A23 to A19 are don’t care ≤ n ≤ 256 Instruction 24-bit address MSB Data byte 2 Data byte MSB MSB Data byte MSB Data byte MSB AI04045 Instructions 25/49 ...
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... A page program (PP) instruction applied to a page that is hardware protected is not executed. Any page program (PP) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 26/49 Figure 13. and Table 15: AC characteristics (75 MHz operation, M45PE40 Table 14: AC ...
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... M45PE40 Figure 13. Page program (PP) instruction sequence Address bits A23 to A19 are don’t care ≤ n ≤ 256 Instruction 24-bit address MSB Data byte 2 Data byte MSB MSB Data byte MSB Data byte MSB AI04044 Instructions 27/49 ...
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... Any page erase (PE) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 14. Page erase (PE) instruction sequence Address bits A23 to A19 are don’t care. 28/49 Figure 14 Instruction 24-bit address 23 22 MSB M45PE40 ) is initiated AI04046 ...
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... M45PE40 6.10 Sector erase (SE) The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL) ...
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... Any deep power-down (DP) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 16. Deep power-down (DP) instruction sequence 30/49 Figure 16 Instruction M45PE40 specified CC1 CC2 before the supply current is reduced Deep power-down mode Standby mode AI03753D ...
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... M45PE40 6.12 Release from deep power-down (RDP) Once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down (RDP) instruction. Executing this instruction takes the device out of the deep power-down mode. The release from deep power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on serial data input (D) ...
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... CC , all operations are disabled and the device does not respond WI VSL modes. is less than the CC PUW threshold. However, the correct operation of is still below V (min). No write, program or CC (min), the device can be CC M45PE40 has elapsed supply. CC ...
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... M45PE40 Figure 18. Power-up timing (max (min) Reset state of the device V WI Table 6. Power-up timing and V Symbol ( (min low VSL CC (1) t Time delay before the first write, program or erase instruction PUW (1) V Write inhibit voltage WI 1. These parameters are characterized only, over the temperature range –40 °C to +85 °C. ...
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... Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx ® ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω 500 Ω). 34/49 Table 7: Absolute maximum ratings Parameter (2) M45PE40 may Min Max Unit –65 150 °C (1) See note ° ...
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... M45PE40 10 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... Input high voltage IH V Output low voltage OL V Output high voltage OH 36/49 Test condition Parameter (in addition to those 0. 0. Min Table 0.9 MHz open / 0.9 MHz open – 0 –100 µA V –0.2 CC M45PE40 Max Unit ± 2 µA ± 2 µA 50 µA 10 µ ...
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... M45PE40 Table 12. AC characteristics (25 MHz operation) Symbol Alt ( CLH ( CLL t t SLCH CSS t CHSL t t DVCH DSU t t CHDX DH t CHSH t SHCH t t SHSL CSH ( SHQZ DIS t t CLQV CLQX HO t WHSL t SHWL ( (2) t RDP ( ( must be greater than or equal Value guaranteed by characterization, not 100% tested in production. ...
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... Page program cycle time (256 bytes) Page program cycle time (n bytes) Page erase cycle time Sector erase cycle time . C (1) Table 8 and Table 9 Min Typ Max D. 200 100 10.2+ n*0.8/256 1.2 5 0.4+ n*0.8/256 M45PE40 Unit MHz MHz µs µ ...
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... M45PE40 Table 14. AC characteristics (50 MHz operation) 50 MHz preliminary data for T9HX technology Test conditions specified in Symbol Alt Clock frequency for the following instructions FAST_READ, PW, PP, PE, SE, DP, RDP WREN, WRDI, RDSR, RDID f Clock frequency for read instructions R ( Clock High time CH CLH ( Clock Low time ...
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... A. For instance, int(12/ int(32/ int(15.3) =16. 40/49 Table 8 Parameter (4) (peak to peak (1) (2) ) and Table 9 Min Typ Max D. 100 100 0.8 3 (7) int(n/8) × 0.025 150 Section 12: Ordering M45PE40 Unit MHz MHz µs µ ...
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... M45PE40 Figure 20. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 21. Write protect setup and hold timing W tWHSL High Impedance Q Figure 22. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tSLCH tCHSH tCHDX tCLCH MSB IN tCH tCLQV DC and AC parameters tSHSL tSHCH tCHCL LSB IN ...
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... Value guaranteed by characterization, not 100% tested in production. Figure 23. Reset AC waveforms S Reset 42/49 Test conditions specified in Parameter Conditions Reset pulse width Chip should have been Chip Select High to deselected before Reset is Reset High de-asserted tSHRH tRLRH Table 8 and Table 9 Min Typ Max 10 10 tRHSL M45PE40 Unit µs ns AI06808 ...
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... M45PE40 11 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 24. VFQFPN8 (MLP8) 8-lead very thin dual flat package no lead, 6 × ...
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... M45PE40 inches Typ Min Max 0.033 0.031 0.039 0.000 0.002 0.026 0.007 0.016 0.014 0.020 0.236 0.226 0.134 0.126 0.142 0.197 ...
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... M45PE40 Figure 25. SO8 wide – 8 lead plastic small outline, 208 mils body width, package outline 1. Drawing is not to scale. Table 18. SO8 wide – 8 lead plastic small outline, 208 mils body width, package mechanical data Symbol millimeters Typ Min Max 2.50 0.00 0.25 1 ...
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... GAUGE PLANE SO-A inches Typ Min 0.004 0.049 0.011 0.007 0.193 0.189 0.236 0.228 0.154 0.150 0.050 – 0.010 0° 0.016 0.041 M45PE40 Max 0.069 0.010 0.019 0.009 0.004 0.197 0.244 0.157 – 0.020 8° 0.050 ...
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... Package available only in T9HX technology. Note: For a list of available options (speed, package, etc.), for further information on any aspect of this device, or when ordering parts operating at 75 MHz (0.11 µm technology, process digit ‘4’), please contact your nearest Numonyx sales office. M45PE40 – (1) Ordering information ...
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... Page write (PW) and values in Table 11: DC CC3 scheme. VCC supply voltage and VSS ground updated and ratings. Table 12: AC characteristics (25 added. mechanical). Plating technology in Table 20: Ordering Section 11: Package mechanical. Figure 3: Bus master and bus, and Section 6.3: Read identification M45PE40 scheme. Page ...
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... M45PE40 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...