M45PE40-VMP6TG NUMONYX, M45PE40-VMP6TG Datasheet - Page 6

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M45PE40-VMP6TG

Manufacturer Part Number
M45PE40-VMP6TG
Description
IC FLASH 4MBIT 75MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r
Datasheet

Specifications of M45PE40-VMP6TG

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Cell Type
NOR
Density
4Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
VFQFPN EP
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
512K
Supply Current
8mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M45PE40-VMP6TG
M45PE40-VMP6TGTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M45PE40-VMP6TG
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
M45PE40-VMP6TG
Manufacturer:
ST
0
Description
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Description
The M45PE40 is a 4-Mbit (512 Kbit x8 bit) serial paged flash memory accessed by a high
speed SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time, using the page write or
page program instruction. The page write instruction consists of an integrated page erase
cycle followed by a page program cycle.
The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes
wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524288 bytes.
The memory can be erased a page at a time, using the page erase instruction, or a sector at
a time, using the sector erase instruction.
Important note
This datasheet details the functionality of the M45PE40 devices, based on the previous T7X
process or based on the current T9HX process (available since August 2007). Delivery of
parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008.
Figure 1.
Logic diagram
Reset
W
D
C
S
V CC
V SS
M45PE40
Q
AI04040C
M45PE40

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