CY7C1381D-100BZC Cypress Semiconductor Corp, CY7C1381D-100BZC Datasheet - Page 8

• Manufacturer Part Number: CY7C1381D-100BZC
• Description: IC SRAM 18MBIT 100MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381D-100BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

deasserted and the IOs must be tri-stated prior to the presen-
tation of data to DQs. As a safety precaution, the data lines are
tri-stated once a write cycle is detected, regardless of the state
of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
asserted active, (2) ADSC is asserted LOW, (3) ADSP is
deasserted HIGH, and (4) the write input signals (GW, BWE,
and BW
active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered
to the memory core The information presented to DQ
be written into the specified address location. Byte writes are
allowed. All IOs are tri-stated when a write is detected, even a
byte write. Since this is a common IO device, the
asynchronous OE input signal must be deasserted and the IOs
must be tri-stated prior to the presentation of data to DQ
a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The
provides an on-chip two-bit wraparound burst counter inside
the SRAM. The burst counter is fed by A
either a linear or interleaved burst order. The burst order is
determined by the state of the MODE input. A LOW on MODE
will select a linear burst sequence. A HIGH on MODE will
select an interleaved burst order. Leaving MODE unconnected
will cause the device to default to a interleaved burst
sequence.
ZZ Mode Electrical Characteristics
Document #: 38-05544 Rev. *F
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
X
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
) indicate a write access. ADSC is ignored if ADSP is
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
Description
1
, CE
2
, and CE
[1:0]
, and can follow
3
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
[2]
[A:D]
are all
s
DD
DD
. As
will
Test Conditions
– 0.2V
– 0.2V
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE
remain inactive for the duration of t
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
Address
Address
A1: A0
A1: A0
First
First
00
01
10
11
00
01
10
11
Address
Address
Second
Second
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
A1: A0
A1: A0
1
, CE
01
00
10
01
10
00
11
11
2t
Min
2
CYC
0
, CE
DD
3
)
[2]
Address
Address
A1: A0
A1: A0
Third
Third
, ADSP, and ADSC must
ZZREC
10
11
00
01
10
11
00
01
2t
2t
Max
80
CYC
CYC
after the ZZ input
Page 8 of 29
Address
Address
Fourth
A1: A0
Fourth
A1: A0
Unit
10
01
00
00
01
10
11
11
mA
ns
ns
ns
ns
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