CY7C1381D-133AXI Cypress Semiconductor Corp, CY7C1381D-133AXI Datasheet

IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC

CY7C1381D-133AXI

Manufacturer Part Number

CY7C1381D-133AXI

Description

IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC

Manufacturer

Cypress Semiconductor Corp

Datasheets

1.CY7C1381D-133AXC.pdf (29 pages)

2.CY7C1381D-133AXC.pdf (29 pages)

3.CY7C1381F-133BGCT.pdf (17 pages)

Specifications of CY7C1381D-133AXI

Format - Memory

RAM

Memory Type

SRAM - Synchronous

Memory Size

18M (512K x 36)

Speed

133MHz

Interface

Parallel

Voltage - Supply

3.135 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Package / Case

100-LQFP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

428-2147
CY7C1381D-133AXI

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C1381D-133AXI

Manufacturer:

Quantity:

21 440

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1381D-133AXI

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1381D-133AXIT

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

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Features

Selection Guide

Cypress Semiconductor Corporation

Document #: 38-05544 Rev. *F

Notes:

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE

• Supports 133 MHz bus operations

• 512K × 36 and 1M × 18 common IO

• 3.3V core power supply (V

• 2.5V or 3.3V IO supply (V

• Fast clock-to-output time

• Provides high performance 2-1-1-1 access rate

• User selectable burst counter supporting Intel

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• CY7C1381D/CY7C1383D available in JEDEC-standard

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

— 6.5 ns (133 MHz version)

interleaved or linear burst sequences

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball

FBGA package. CY7C1381F/CY7C1383F available in

Pb-free and non Pb-free 119-ball BGA package

are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

DDQ

)

•

198 Champion Court

Pentium

133 MHz

210

6.5

Functional Description

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a

3.3V, 512K x 36 and 1M x 18 synchronous flow through

SRAMs,

microprocessors with minimum glue logic. Maximum access

delay from clock rise is 6.5 ns (133 MHz version). A 2-bit

on-chip counter captures the first address in a burst and

increments the address automatically for the rest of the burst

access. All synchronous inputs are gated by registers

controlled by a positive edge triggered clock input (CLK). The

synchronous inputs include all addresses, all data inputs,

address pipelining chip enable (CE

enables (CE

and ADV), write enables (BW

(GW). Asynchronous inputs include the output enable (OE)

and the ZZ pin.

The

allows interleaved or linear burst sequences, selected by the

MODE input pin. A HIGH selects an interleaved burst

sequence, while a LOW selects a linear burst sequence. Burst

accesses can be initiated with the processor address strobe

(ADSP) or the cache controller address strobe (ADSC) inputs.

Address

advancement (ADV) input.

Addresses and chip enables are registered at rising edge of

clock when address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

The

operates from a +3.3V core power supply while all outputs

operate with a +2.5V or +3.3V supply. All inputs and outputs

are JEDEC-standard and JESD8-5-compatible.

•

CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F

advancement

San Jose

designed

and CE

100 MHz

175

8.5

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

CA 95134-1709

[2]

), burst control inputs (ADSC, ADSP,

is controlled

interface

[1]

, and BWE), and global write

Revised Feburary 07, 2007

), depth-expansion chip

with

•

Unit

the address

408-943-2600

high-speed

[+] Feedback

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