CY7C1381D-133AXI Cypress Semiconductor Corp, CY7C1381D-133AXI Datasheet

IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC

CY7C1381D-133AXI

Manufacturer Part Number

CY7C1381D-133AXI

Description

IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC

Manufacturer

Cypress Semiconductor Corp

Datasheets

1.CY7C1381D-133AXC.pdf (29 pages)

2.CY7C1381D-133AXC.pdf (29 pages)

3.CY7C1381F-133BGCT.pdf (17 pages)

Specifications of CY7C1381D-133AXI

Format - Memory

RAM

Memory Type

SRAM - Synchronous

Memory Size

18M (512K x 36)

Speed

133MHz

Interface

Parallel

Voltage - Supply

3.135 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Package / Case

100-LQFP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

428-2147
CY7C1381D-133AXI

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Features

■

Notes

Cypress Semiconductor Corporation

Document #: 38-06037 Rev. *E

1. BUSY is an output in master mode and an input in slave mode.

2. Interrupt: push-pull output and requires no pull-up resistor.

True Dual-Ported Memory Cells that Enable Simultaneous

Reads of the Same Memory Location

4K x 8 Organization (CY7C138)

4K x 9 Organization (CY7C139)

0.65-micron CMOS for Optimum Speed and Power

High Speed Access: 15 ns

Low Operating Power: I

Fully Asynchronous Operation

Automatic Power Down

TTL Compatible

Expandable Data Bus to 32/36 Bits or more using

Master/Slave Chip Select when using more than one

Device

On-Chip Arbitration Logic

Semaphores Included to Permit Software Handshaking

between Ports

INT Flag for Port-to-Port Communication

Available in 68-pin PLCC

Pb-free Packages Available

Logic Block Diagram

(7C139)I/O

BUSY

= 160 mA (max.)

R/W

I/O

[1, 2]

11L

INT

SEM

[2]

•

198 Champion Court

ADDRESS

DECODER

R/W

CONTROL

I/O

Functional Description

The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and

4K x 9 dual-port static RAMs. Various arbitration schemes are

included on the CY7C138/9 to handle situations when multiple

processors access the same piece of data. Two ports are

provided permitting independent, asynchronous access for

reads and writes to any location in memory. The CY7C138/9 can

be used as a standalone 8/9-bit dual-port static RAM or multiple

devices can be combined to function as a 16/18-bit or wider

master/slave dual-port static RAM. An M/S pin is provided for

implementing 16/18-bit or wider memory applications without the

need for separate master and slave devices or additional

discrete logic. Application areas include interprocessor/multipro-

cessor designs, communications status buffering, and dual-port

video/graphics memory.

Each port has independent control pins: chip enable (CE), read

or write enable (R/W), and output enable (OE). Two flags are

provided on each port (BUSY and INT). BUSY signals that the

port is trying to access the same location currently being

accessed by the other port. The interrupt flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from one

port to the other to indicate that a shared resource is in use. The

semaphore logic is comprised of eight shared latches. Only one

side can control the latch (semaphore) at any time. Control of a

semaphore indicates that a shared resource is in use. An

automatic power down feature is controlled independently on

each port by a chip enable (CE) pin or SEM pin.

ARBITRATION

SEMAPHORE

INTERRUPT

4K x 8/9 Dual-Port Static RAM

MEMORY

ARRAY

M/S

•

San Jose

CONTROL

I/O

R/W

DECODER

ADDRESS

CA 95134-1709

with Sem, Int, Busy

CY7C138, CY7C139

INT

SEM

[2]

Revised June 03, 2009

R/W

I/O

BUSY

•

11R

(7C139)

[1, 2]

408-943-2600

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