CY7C1381D-133AXI Cypress Semiconductor Corp, CY7C1381D-133AXI Datasheet - Page 6

IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC

CY7C1381D-133AXI

Manufacturer Part Number
CY7C1381D-133AXI
Description
IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp

Specifications of CY7C1381D-133AXI

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
18M (512K x 36)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-2147
CY7C1381D-133AXI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1381D-133AXI
Manufacturer:
AD
Quantity:
21 440
Part Number:
CY7C1381D-133AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C1381D-133AXIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Characteristics
Switching Waveforms
Notes
Document #: 38-06037 Rev. *E
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
10. At any temperature and voltage condition for any device, t
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
15. t
HZWE
LZWE
WDD
DDD
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
INS
INR
SOP
SWRD
SPS
BUSY TIMING
INTERRUPT TIMING
SEMAPHORE TIMING
Parameter
and 30-pF load capacitance.
BDD
DATA OUT
ADDRESS
[15]
[13]
[13]
[11,12]
[11,12]
is a calculated parameter and is the greater of t
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Setup for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
[14]
PREVIOUS DATA VALID
[14]
Description
t
OHA
Figure 3. Read Cycle No. 1 (Either Port Address Access)
Over the Operating Range
t
WDD
AA
– t
HZCE
PWE
is less than t
(actual) or t
Min
13
10
3
5
0
5
5
7C138-15
7C139-15
LZCE
DDD
Note 15
t
RC
[9]
Max
10
30
25
15
15
15
15
15
15
– t
and t
(continued)
SD
HZOE
(actual).
Min
20
10
3
5
0
5
5
is less than t
7C138-25
7C139-25
Note 15
Max
15
50
30
20
20
20
20
25
25
LZOE
.
Min
DATA VALID
30
15
3
5
0
5
5
7C138-35
7C139-35
[16, 17]
Note 15
CY7C138, CY7C139
Max
20
60
35
20
20
20
20
25
25
Min
40
20
3
5
0
5
5
7C138-55
7C139-55
Note 15
Max
25
70
40
45
40
40
35
30
30
Page 6 of 17
Unit
OI
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/I
OH
[+] Feedback

Related parts for CY7C1381D-133AXI