CY7C1381D-133AXI Cypress Semiconductor Corp, CY7C1381D-133AXI Datasheet - Page 7

• Manufacturer Part Number: CY7C1381D-133AXI
• Description: IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381D-133AXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2147; CY7C1381D-133AXI

Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
The
supports secondary cache in systems utilizing a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BW
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous chip selects (CE
asynchronous output enable (OE) provide for easy bank
Document #: 38-05544 Rev. *F
MODE
V
V
V
V
TDO
TDI
TMS
TCK
NC
V
DD
DDQ
SS
SSQ
SS
E
/DNU
) and byte write select (BW
Name
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
CDV
®
JTAG serial output
JTAG serial input
JTAG serial input
IO Power Supply Power supply for the IO circuitry.
) is 6.5 ns (133 MHz device).
(continued)
Power Supply
and i486™ processors. The linear burst
Synchronous
Synchronous
Synchronous
Ground/DNU
Input-Static
IO Ground
Ground
JTAG-
Clock
IO
–
X
) inputs. A global write
Selects burst order. When tied to GND selects linear burst sequence. When tied to V
or left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.
Power supply inputs to the core of the device.
Ground for the core of the device.
Ground for the IO circuitry.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin can be left unconnected. This pin is not available
on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be left floating or connected to V
resistor. This pin is not available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V
No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G
are address expansion pins and are not internally connected to the die.
This pin can be connected to ground or can be left floating.
1
, CE
2
, CE
3
[2]
) and an
SS
. This pin is not available on TQFP packages.
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter and/or control logic, and later presented to the
memory core. If the OE input is asserted LOW, the requested
data will be available at the data outputs with a maximum to
t
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BW
cycle. If the write inputs are asserted active (see
for Read/Write
indicate a write) on the next clock rise, the appropriate data will
be latched and written into the device. Byte writes are allowed.
All IOs are tri-stated during a byte write. As this is a common
IO device, the asynchronous OE input signal must be
CDV
after clock rise. ADSP is ignored if CE
Description
E
[4, 9]
, and BW
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
on page 10
X
) are ignored during this first clock
1
, CE
1
for appropriate states that
, CE
2
, CE
DD
2
, and CE
3
DD
[2]
through a pull up
1
. This pin is not
is HIGH.
are all asserted
Page 7 of 29
Truth Table
3
[2]
are all
DD
1
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