CY7C1381D-133AXI Cypress Semiconductor Corp, CY7C1381D-133AXI Datasheet - Page 13

• Manufacturer Part Number: CY7C1381D-133AXI
• Description: IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381D-133AXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2147; CY7C1381D-133AXI

TAP Timing
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to
drive the output bus. When LOW, this bit will place the output
bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
TAP AC Switching Characteristics
Over the Operating Range
Notes:
Document #: 38-05544 Rev. *F
10. t
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
11. Test conditions are specified using the load in TAP AC test conditions. t
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
CS
and t
Parameter
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
Test Mode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
(TCK)
(TDI)
[10, 11]
1
t TMSS
t TDIS
Description
2
t TMSH
t TDIH
t TH
DON’T CARE
R
t
TL
/t
F
= 1 ns.
3
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t CYC
UNDEFINED
4
t TDOX
t TDOV
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
5
Min
50
20
20
0
5
5
5
5
5
5
6
Max
20
10
Page 13 of 29
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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