CY7C1381D-133AXI Cypress Semiconductor Corp, CY7C1381D-133AXI Datasheet - Page 15

• Manufacturer Part Number: CY7C1381D-133AXI
• Description: IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381D-133AXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2147; CY7C1381D-133AXI

Identification Register Definitions
Scan Register Sizes
Identification Codes
Document #: 38-05544 Rev. *F
Note:
13. Bit #24 is “1” in the register definitions for both 2.5V and 3.3V versions of this device.
Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18) 119-BGA
Device Width (23:18) 165-FBGA
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Instruction Bypass
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Instruction Field
Register Name
[13]
Code
000
001
010
011
100
101
110
111
CY7C1381D/CY7C1381F
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use. This instruction is reserved for future use.
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect SRAM operation.
Do Not Use. This instruction is reserved for future use.
Do Not Use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
00000110100
(512K × 36)
101001
000001
100101
01011
000
1
CY7C1383D/CY7C1383F
Bit Size (×36)
00000110100
(1M × 18)
101001
000001
010101
32
85
89
01011
3
1
000
1
Description
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Describes the version number.
Reserved for internal use.
Defines the memory type and
architecture.
Defines the memory type and
architecture.
Defines the width and density.
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID
register.
Description
Bit Size (×18)
32
85
89
3
1
Page 15 of 29
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