CY7C1370D-167AXI Cypress Semiconductor Corp, CY7C1370D-167AXI Datasheet - Page 10

• Manufacturer Part Number: CY7C1370D-167AXI
• Description: IC SRAM 18MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1370D-167AXI

• Memory Size: 18M (512K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 3.4 ns
• Maximum Clock Frequency: 167 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 275 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2136; CY7C1370D-167AXI

Truth Table
The Truth Table for CY7C1370D and CY7C1372D follows
Notes
Document Number: 38-05555 Rev. *K
Deselect cycle
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/write abort (begin burst)
Write abort (continue burst)
Ignore clock edge (stall)
Sleep mode
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
2. Write is defined by WE and BW
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
inactive or when the device is deselected, and DQ
Operation
X
. See Write Cycle Description table for details.
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
Address
Used
s
= data when OE is active.
CE
H
X
X
L
X
L
X
L
L
X
X
X
.[1, 2, 3, 4, 5, 6, 7]
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
ADV/LD
H
H
H
H
H
X
X
L
L
L
L
L
WE
H
H
X
X
X
X
L
X
L
X
X
X
BW
H
H
X
X
X
X
X
X
L
L
X
X
x
X
X
L
L
H
H
X
X
X
X
X
X
CY7C1370D, CY7C1372D
OE
L
L
L
L
L
L
L
L
L
L
H
X
CEN
s
and DQP
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
X
CLK
X
= Three-state when OE is
Data out (Q)
Data out (Q)
Data in (D)
Data in (D)
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Page 10 of 29
DQ
–
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