MAX807NCPE Maxim Integrated, MAX807NCPE Datasheet - Page 11

• Manufacturer Part Number: MAX807NCPE
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX807L, MAX807M, MAX807Nr

Specifications of MAX807NCPE

• Number Of Voltages Monitored: 1
• Monitored Voltage: 4.575 V
• Undervoltage Threshold: 4.5 V
• Overvoltage Threshold: 4.65 V
• Output Type: Active High, Active Low
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIP N
• Chip Enable Signals: Yes
• Maximum Power Dissipation: 842 mW
• Minimum Operating Temperature: 0 C
• Power Fail Detection: Yes
• Supply Current (typ): 70 uA
• Supply Voltage - Min: 0 V

(see the Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and 50pF of load
capacitance (Figure 8). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low output-impedance driver.
In the enabled mode, the impedance of CE OUT is equiv-
alent to 75Ω in series with the source driving CE IN. In the
disabled mode, the 75Ω transmission gate is off and CE
OUT is actively pulled to the higher of V
source turns off when the transmission gate is enabled.
The low-line comparator monitors V
voltage typically 52mV above the reset threshold, with
13mV of hysteresis. Use LOW LINE to provide a non-
maskable interrupt (NMI) to the µP when power begins
to fall to initiate an orderly software shutdown routine.
In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the shutdown routine once the low-line warning is
encountered, and before reset asserts. If the system must
contend with a more rapid V
the main battery is disconnected, a DC-DC converter
shuts down, or a high-side switch is opened during
normal operation—use capacitance on the V
provide time to execute the shutdown routine (Figure 9).
First calculate the worst-case time required for the
system to perform its shutdown routine. Then, with the
Figure 7. Reset and Chip-Enable Timing
THRESHOLD
CE OUT
RESET
RESET
RESET
CE IN
V
CC
Full-Featured µP Supervisory Circuit with
______________________________________________________________________________________
Low-Line Comparator
CC
fall time—such as when
28µs
26µs
Chip-Enable Output
CC
CC
with a threshold
or V
CC
BATT
26µs
line to
. This
worst-case shutdown time, the worst-case load current,
and the minimum low-line to reset threshold (V
calculate the amount of capacitance required to allow the
shutdown routine to complete before reset is asserted:
where t
plete the shutdown routine, and includes the V
low-line propagation delay; and where I
rent being drained from the capacitor, V
line to reset threshold.
Figure 8. CE Propagation Delay Test Circuit
Figure 9. Using LOW LINE to Provide a Power-Fail Warning to
the µP
±1.5% Reset Accuracy
50Ω DRIVER
REGULATOR
C
SHDN
HOLD
C
> I
HOLD
LOAD
is the time required for the system to com-
C
HOLD
V
4.5V to 5.5V
x t
LR
= (I
SHDN
LOAD
CE IN
V
MAX807
V
RST
x t
GND
CC
V
CC
MAX
MAX807
SHDN
GND
CE OUT
LOW LINE
) / V
LR
LOAD
LR
(min)
50pF
C
is the low-
LOAD
is the cur-
TO µP NMI
LR(min)
CC
11
to
),