CY7C1315JV18-300BZC Cypress Semiconductor Corp, CY7C1315JV18-300BZC Datasheet - Page 6

• Manufacturer Part Number: CY7C1315JV18-300BZC
• Description: IC SRAM SYNC 18KB QDR2 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1315JV18-300BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Document Number: 001-12562 Rev. *D
D
WPS
NWS
NWS
BWS
BWS
BWS
BWS
A
Q
RPS
C
C
K
K
Pin Name
[x:0]
[x:0]
0
1
2
3
0
1
,
,
,
,
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input Clock
Input Clock
Input Clock
Input Clock
Output-
Input-
Input-
Input-
Input-
Input-
Input-
IO
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1311JV18 − D
CY7C1911JV18 − D
CY7C1313JV18 − D
CY7C1315JV18 − D
Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
Nibble Write Select 0, 1 − Active LOW (CY7C1311JV18 Only). Sampled on the rising edge of the K
and K clocks during write operations. Used to select which nibble is written into the device during the
current portion of the write operations. Nibbles not written remain unaltered.
NWS
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1911JV18 − BWS
CY7C1313JV18 − BWS
CY7C1315JV18 − BWS
BWS
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2M x 8 (4 arrays each of 512K x 8) for CY7C1311JV18, 2M x 9 (4 arrays each of 512K x 9) for
CY7C1911JV18,1M x 18 (4 arrays each of 256K x 18) for CY7C1313JV18 and 512K x 36 (4 arrays each
of 128K x 36) for CY7C1315JV18. Therefore, only 19 address inputs are needed to access the entire
memory array of CY7C1311JV18 and CY7C1911JV18, 18 address inputs for CY7C1313JV18 and 17
address inputs for CY7C1315JV18. These inputs are ignored when the appropriate port is deselected.
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q
CY7C1311JV18 − Q
CY7C1911JV18 − Q
CY7C1313JV18 − Q
CY7C1315JV18 − Q
Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the C clock. Each read access consists of a burst of four sequential transfers.
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C are used together to deskew the flight times of various devices on the board back to
the controller. See
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C are used together to deskew the flight times of various devices on the board back to
the controller. See
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
3
0
controls D
controls D
[35:27].
[3:0]
Application Example
Application Example
[7:0]
[8:0]
[7:0]
[8:0]
[17:0]
[35:0]
[17:0]
[35:0]
and NWS
0
0
0
controls D
controls D
controls D
[x:0]
1
when in single clock mode.
[x:0]
controls D
when in single clock mode. All accesses are initiated on the rising
[8:0]
[8:0]
[8:0]
, BWS
and BWS
on page 10 for further details.
on page 10 for further details.
[7:4]
Pin Description
1
.
controls D
[x:0]
1
CY7C1313JV18/CY7C1315JV18
controls D
CY7C1311JV18/CY7C1911JV18
are automatically tri-stated.
[17:9]
[17:9].
, BWS
2
controls D
[26:18]
and
Page 6 of 27
[x:0]
.
[+] Feedback