IDT70V28L15PFG IDT, Integrated Device Technology Inc, IDT70V28L15PFG Datasheet - Page 11

IC SRAM 1MBIT 15NS 100TQFP

IDT70V28L15PFG

Manufacturer Part Number
IDT70V28L15PFG
Description
IC SRAM 1MBIT 15NS 100TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT70V28L15PFG

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
1M (64K x 16)
Speed
15ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Density
1Mb
Access Time (max)
15ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
16b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
235mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
16b
Number Of Words
64K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
70V28L15PFG
800-1393

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70V28L15PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT70V28L15PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT70V28L15PFGI
Manufacturer:
THOMBETT
Quantity:
3 072
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
DATA
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = V
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. t
DATA
IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM
ADDR
ADDR
WH
WB
BUSY
L
R/W
OUT "B"
must be met for both BUSY input (SLAVE) and output (MASTER).
is only for the 'slave' version.
= CE
IN "A"
IL
"A"
"A"
"B"
"B"
for the reading port.
R
IL
= V
(slave), BUSY is an input. Then for this example BUSY
IL,
refer to Chip Enable Truth Table.
t
APS
(1)
BUSY
R/W
R/W
"A"
"B"
"B"
"B"
, until BUSY
APS
is ignored for M/S = V
"B"
goes HIGH.
t
WB
"A"
(3)
= V
t
BAA
IH
IL
and BUSY
(SLAVE).
MATCH
t
WC
11
t
WP
(2)
"B"
input is shown above.
t
WP
Industrial and Commercial Temperature Ranges
MATCH
IL
t
DW
t
WDD
)
VALID
t
WH
(1)
4849 drw 12
t
DDD
(3)
.
t
BDA
t
DH
IH
)
4849 drw 11
t
BDD
(2,4,5)
VALID

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