CYD18S18V18-200BBAXC Cypress Semiconductor Corp, CYD18S18V18-200BBAXC Datasheet
CYD18S18V18-200BBAXC
Specifications of CYD18S18V18-200BBAXC
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CYD18S18V18-200BBAXC Summary of contents
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... K × 36 (CYD04S36V18) ❐ 2-Mbit × 36 (CYD02S36V18) ❐ FullFlex18 family ■ 36-Mbit × 18 (CYD36S18V18) ❐ 18-Mbit × 18 (CYD18S18V18) ❐ 9-Mbit: 512 K × 18 (CYD09S18V18) ❐ 4-Mbit: 256 K × 18 (CYD04S18V18) ❐ Built in deterministic access control to manage address ■ collisions Deterministic flag output upon collision detection ❐ ...
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... L Notes 1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and CYD04S36V18 devices have 17 address bits. The CYD04S72V18 and CYD02S36V18 have 16 address bits. ...
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Contents Selection Guide ................................................................ 9 Pin Definitions .................................................................. 9 Variable Impedance Matching ....................................... 12 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 18 Maximum Ratings ........................................................... 19 Operating Range ............................................................. 19 Power Supply Requirements ......................................... 19 Electrical Characteristics ............................................... 19 Electrical ...
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Figure 1. FullFlex72 SDR 484-ball BGA Pinout (Top View DNU DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L B DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L C DQ65L DQ64L VSS VSS DQ56L DQ53L DQ50L D ...
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Figure 2. FullFlex36 SDR 484-ball BGA Pinout (Top View DNU DNU DNU DNU DNU DQ33L DQ30L B DNU DNU DNU DNU DNU DQ34L DQ31L C DNU DNU VSS VSS DNU DQ35L DQ32L D ...
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Figure 3. FullFlex18 SDR 484-ball BGA Pinout (Top View DNU DNU DNU DNU DNU DNU B DNU DNU DNU DNU DNU DNU C DNU DNU VSS VSS DNU DNU D DNU DNU VSS ...
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Figure 4. FullFlex36 SDR 256-ball BGA (Top View DQ32L DQ30L DQ28L DQ26L DQ24L A DQ33L DQ31L DQ29L DQ27L DQ25L B DQ34L DQ35L RETL INTL CQ1L C A0L A1L WRPL VREFL FTSELL D A2L A3L CE0L ...
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Figure 5. FullFlex18 SDR 256-ball BGA (Top View DNU DNU DNU DQ17L DQ16L B DNU DNU DNU DNU DQ15L C DNU DNU RETL INTL CQ1L D A0L A1L WRPL VREFL FTSELL E A2L A3L ...
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... SDR mode with two pipelined stages. 22. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and CYD04S36V18 devices have 17 address bits ...
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... RET RET Port counter retransmit input. Assert this pin LOW to reload the initial address for repeated L R access to the same segment of memory. VREF VREF Port external HSTL IO reference input. This pin is left DNU when HSTL is not used ...
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Selectable IO Standard The FullFlex device families offer the option to choose one of the four port standards for the device. Each port independently selects standards from single ended HSTL class I, single ended LVTTL, 2.5 V LVCMOS, or 1.8 ...
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When a busy readback is performed, the address of the first match that happens at least two clocks cycles after the busy readback is saved into the busy address register. Table 3. t Timing ...
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... Note 27. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and CYD04S36V18 devices have 17 address bits ...
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Table 7. Burst Counter and Mask Register Control Operations The burst counter and mask register control operation for any port follows. C MRST CNTRST CNT/MSK CNTEN ADS RET ...
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... An internal Note 30. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and CYD04S36V18 devices have 17 address bits ...
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... Counter Note 31. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and CYD04S36V18 devices have 17 address bits. The CYD04S72V18 and CYD02S36V18 have 16 address bits. ...
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... Don’t Care, “H” = HIGH, “L” = LOW. 37. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and CYD04S36V18 devices have 17 address bits ...
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... Details of the boundary scan length is found in the BSDL file for the device. Document Number: 38-06082 Rev. *J Table 9. JTAG IDCODE Register Definitions Part Number L CYD36S72V18 . When asserted RS CYD36S36V18 CYD36S18V18 CYD18S72V18 CYD18S36V18 CYD18S18V18 CYD09S72V18 CYD09S36V18 CYD09S18V18 CYD04S72V18 CYD04S36V18 CYD04S18V18 CYD02S36V18 Table 10. Scan Registers Sizes Register Name Instruction Bypass ...
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Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage temperature............................... –65 ° 150 °C Ambient temperature with power applied .......................................... –55 ° 125 °C Supply voltage ...
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Electrical Characteristics Over the Operating Range (continued) Parameter Description Output HIGH voltage READY (V = Min –24 mA) DDIO Min –12 mA) DDIO Min –12 mA) ...
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Electrical Characteristics Over the Operating Range Parameter Description I Operating current Max mA) CORE OUT outputs disabled Document Number: 38-06082 Rev. *J –200 Configuration Typ Max 512 K × 72 Commercial 1440 1800 Industrial ...
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Electrical Characteristics Over the Operating Range (continued) Parameter Description I Standby current SB1 (both ports TTL Level) and MAX Document Number: 38-06082 Rev. *J –200 Configuration Typ Max 512 ...
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Electrical Characteristics Over the Operating Range (continued) Parameter Description I Standby current SB2 (one port TTL or CMOS level) MAX Document Number: 38-06082 Rev. *J –200 Configuration Typ ...
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... Commercial Industrial 256 K × 36 Commercial Industrial 512 K × 18 Commercial Industrial 64 K × 72 Commercial Industrial 128 K × 36 Commercial Industrial 256 K × 18 Commercial Industrial Packages CYD18S18V18 CYD09S18V18 CYD04S18V18 FullFlex All Speed Bins Typ Max 410 590 460 700 410 590 460 700 410 ...
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AC Test Load and Waveforms R=250 Ohm R=250 Ohm Document Number: 38-06082 Rev. *J Figure 9. Output Test Load for LVTTL/CMOS VTH = 1.5V for LVTTL VTH = 50% VDDIO for 2.5V CMOS VTH = 50% VDDIO for 1.8V CMOS ...
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Switching Characteristics Over the Operating Range Table 13. SDR Mode, Signals Affected by DLL Description Parameter [48 rise to DQ valid for pipelined CD2 mode [48 rise to CQ rise CCQ [43, 48 rise ...
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Table 14. SDR Mode (continued) Parameter Description [49 high Z OHZ t C rise to DQ valid for flow through mode CD1 (LowSPD = rise to address readback valid for flow through CA1 mode ...
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Table 15. Master Reset Timing Parameter Description t Power-up time PUP t Master reset pulse width RS t Master reset recovery time RSR t Master reset to outputs inactive/Hi Z RSF [55] t Master reset release to port ready RDY ...
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Switching Waveforms Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO V CORE t PUP MRST C READY All Address & Data All Other Inputs Note 57. READY is a wired OR capable output with a ...
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Switching Waveforms (continued) t CYC SAC R n+1 2 Pipelined stages x Figure 15. WRITE Cycle for Pipelined and Flow through Modes t CYC C CE ...
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Switching Waveforms (continued) Figure 16. READ with Address Counter Advance for Pipelined Mode t CYC Internal A A Address n n+1 ADS CNTEN x-1 x Figure 17. READ with Address Counter Advance for ...
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Switching Waveforms (continued) Figure 18. Port-to-Port WRITE–READ for Pipelined Mode t CYC Left Port R Right Port t CCS CYC R/W R ...
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Switching Waveforms (continued) Figure 20. OE Controlled WRITE for Pipelined Mode t CYC x+1 x x-1 x Figure 21. OE Controlled WRITE for Flow through Mode t CYC ...
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Switching Waveforms (continued) Figure 22. Byte-Enable READ for Pipelined Mode t CYC n+1 R/W BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0 DQ 63:71 DQ 54:62 DQ 45:53 DQ 36:44 DQ 27:35 DQ 18:26 DQ ...
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Switching Waveforms (continued) Figure 23. Port-to-Port WRITE-to-READ for Flow through Mode LID D ...
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Switching Waveforms (continued) Figure 24. Busy Address Readback for Pipelined and Flow through Modes, CNT/MSK = RET = LOW t CYC C Internal A A match+2 match+3 Address BUSY CNTEN ADS External Address Pipelined External Address Flow through t CY ...
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Switching Waveforms (continued) Figure 26. READ-to-WRITE for Pipelined Mode ( CYC SAC HAC R/W t CKLZ2 DQ DQ x-2 x CD2 Figure 27. ...
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Switching Waveforms (continued) Figure 28. Read-to-Write-to-Read for Flow through Mode (OE = LOW) t CYC SAC HAC R ...
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Switching Waveforms (continued) Figure 29. Read-to-Write-to-Read for Flow through Mode (OE Controlled ...
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Switching Waveforms (continued) Figure 30. BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow through Modes, Clock Timing Violates t Port R/W BUSY < t CCS Port R/W BUSY Figure 31. BUSY Timing, WRITE-WRITE Collision ...
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Switching Waveforms (continued) Figure 32. Read with Echo Clock for Pipelined Mode (CQEN = HIGH SAC n+1 CQ0 CQ0 t CCQ CQ1 CQ1 x-1 x Document Number: 38-06082 Rev. ...
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Switching Waveforms (continued) t CYC MAX INT R t SINT Document Number: 38-06082 Rev. *J Figure 33. Mailbox Interrupt Output t ...
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Ordering Information 512 K × 72 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S72V18 Dual Port SRAM Speed Ordering Code (MHz) 200 CYD36S72V18-200BGXC 167 CYD36S72V18-167BGXI 167 CYD36S72V18-167BGI 256 K × 72 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S72V18 Dual Port SRAM Speed Ordering ...
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Ordering Information (continued) 256 K × 36 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S36V18 Dual Port SRAM Speed Ordering Code (MHz) 200 CYD09S36V18-200BBXC 200 CYD09S36V18-200BBXI 167 CYD09S36V18-167BBXC 64 K × 36 (2-Mbit) 1 1.5 V Synchronous CYD02S36V18 Dual Port ...
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... K × 18 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S18V18 Dual Port SRAM Speed Ordering Code (MHz) 200 CYD36S18V18-200BGXC 167 CYD36S18V18-167BGXC 167 CYD36S18V18-167BGXI 1024 K × 18 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S18V18 Dual Port SRAM Speed Ordering Code MHz) 200 CYD18S18V18-200BBAXI 200 CYD18S18V18-200BBAI 167 CYD18S18V18-167BBAXI 512 K × 18 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S18V18 Dual Port SRAM ...
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Package Diagrams Figure 34. 256-ball FPBGA (17 × 17 mm), 51-85108 Document Number: 38-06082 Rev. *J FullFlex 51-85108 *H Page [+] Feedback ...
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Package Diagrams Figure 35. 484-ball PBGA (23 mm × × 2.03 mm), 51-85218 Document Number: 38-06082 Rev. *J FullFlex 51-85218 *A Page [+] Feedback ...
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... FPBGA fine pitch ball gird array HSTL high speed transceiver logic I/O input/output SDR single data rate SRAM static random access memory TCK test clock TDI test data in TDO test data out TMS test mode select VIM variable impedance matching Document Number: 38-06082 Rev ...
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... Updated the Package Type for the CYD36S18V18 parts Updated the Package Type for the CYD36S18V18 parts Updated the Package Type for the CYD18S18V18 parts Updated the Package Type for the CYD18S36V18 parts Included the Package Diagram for the 256-Ball FBGA ( mm) BW256 ...
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Document History Page Document Title: FullFlex™ Synchronous SDR Dual Port SRAM Document Number: 38-06082 ECN NO. Submission Orig. of REV. Date Change *C 402238 SEE ECN *D 458131 SEE ECN *E 470031 SEE ECN *F 500001 SEE ECN *G 627539 ...
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Document History Page Document Title: FullFlex™ Synchronous SDR Dual Port SRAM Document Number: 38-06082 ECN NO. Submission Orig. of REV. Date Change *H 2505003 See ECN *I 2898491 07/01/2010 *J 2995098 07/28/2010 Document Number: 38-06082 Rev. *J Description of Change ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...