93LC56BT-E/MS Microchip Technology, 93LC56BT-E/MS Datasheet - Page 12

• Manufacturer Part Number: 93LC56BT-E/MS
• Description: IC EEPROM 2KBIT 3MHZ 8MSOP
• Manufacturer: Microchip Technology

Specifications of 93LC56BT-E/MS

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (128 x 16)
• Speed: 2MHz, 3MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
3.0
TABLE 3-1:
3.1
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle that is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to Clock High Time (T
Clock Low Time (T
master freedom in preparing opcode, address and
data.
CLK is a “don’t care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
DS21794F-page 12
CS
CLK
DI
DO
V
ORG/NC
NC
V
SS
CC
Name
PIN DESCRIPTIONS
Chip Select (CS)
Serial Clock (CLK)
PIN DESCRIPTIONS
CKL
MSOP/TSSOP/
SOIC/PDIP/
). This gives the controlling
DFN
1
2
3
4
5
6
7
8
CSL
SOT-23
) between
CKH
—
—
5
4
3
1
2
6
) and
Rotated SOIC
data bits before an instruction is executed. CLK and DI
then become “don’t care” inputs waiting for a new Start
condition to be detected.
3.3
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (T
positive edge of CLK).
This pin also provides Ready/
during erase and write cycles. Ready/
mation is available on the DO pin if CS is brought high
after being low for minimum Chip Select low time (T
and an erase or write operation has been initiated.
The Status signal is not available on DO if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
3.5
When the ORG pin is connected to V
(x16) memory organization is selected. When the ORG
pin is tied to V
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX56A devices are always (x8) organization and
93XX56B devices are always (x16) organization.
3
4
5
6
7
8
1
2
Note:
Data In (DI)
Data Out (DO)
Organization (ORG)
Chip Select
Serial Clock
Data In
Data Out
Ground
Organization/93XX56C
No Internal Connection/93XX56A/B
No Internal Connection
Power Supply
After a programming cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
SS
or Logic LO, the (x8) memory
© 2008 Microchip Technology Inc.
Function
Busy
Busy
status information
CC
Busy
status from DO.
or Logic HI, the
PD
status infor-
after the
CSL
)