AT45DB011D-SH-T Atmel, AT45DB011D-SH-T Datasheet
AT45DB011D-SH-T
Specifications of AT45DB011D-SH-T
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AT45DB011D-SH-T Summary of contents
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... Green (Pb/Halide-free/RoHS Compliant) Packaging Options 1. Description The AT45DB011D is a 2.7V, serial-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB011D supports RapidS serial interface for applications requiring very high speed operations. RapidS serial interface is SPI compatible for frequencies MHz ...
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... To allow for simple in-system reprogrammability, the AT45DB011D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB011D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
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... The metal pad on the bottom of the UDFN package is floating. This pad can be a “No Connect” or connected to GND. 3. Block Diagram WP PAGE (256/264 BYTES) BUFFER (256/264 BYTES) SCK CS RESET VCC GND 3639H–DFLASH–04/09 Figure 2- GND 7 6 VCC 5 WP FLASH MEMORY ARRAY I/O INTERFACE SI (1) UDFN Top View SCK GND 2 7 RESET VCC ...
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... Memory Array To provide optimal flexibility, the memory array of the AT45DB011D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis ...
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... When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with cross- ing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array ...
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... The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is AT45DB011D 6 specification. The Continuous Array Read bypasses the data CAR1 ...
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... A8) that specify the page in the main memory to be written and 8 don’t care bits. When a low-to-high transition occurs on the CS pin, the part 3639H– ...
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... CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed and should take place in a maximum time of t this time, the status register will indicate that the part is busy. AT45DB011D 8 . During this time, the status register will indicate that the part is busy. ...
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... Sector Erase The Sector Erase command can be used to individually erase any sector in the main memory. There are 4 sectors and only one sector can be erased at one time. To perform sector 0a or sec- tor 0b erase for the DataFlash standard page size (264 bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of 5 don’ ...
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... Only those sectors that are not protected or locked down will be erased. The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. Command Chip Erase Figure 7-1. AT45DB011D 10 PA5/ PA4/ PA3/ PA2/ A13 ...
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... When there is a low-to-high transi- tion on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. Both the erase and the program- ming of the page are internally self-timed and should take place in a maximum time of t During this time, the status register will indicate that the part is busy ...
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... Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro- tection is desired and if the WP pin is not used. AT45DB011D 12 Byte 1 3DH Enable Sector Protection ...
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Hardware Controlled Protection Sectors specified for protection in the Sector Protection Register and the Sector Protection Reg- ister itself can be protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted ...
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... Sector Protection Register. Table 9-2. Sector Number Protected Unprotected Table 9-3. Sectors 0a, 0b Unprotected Protect Sector 0a Protect Sector 0b (Page 8-127) Protect Sectors 0a (Page 0-7), 0b (Page 8-127) Note: AT45DB011D 14 Sector Protection Register Sector 0 (0a, 0b) 0a (Page 0-7) Bit (1) 1. The default value for bytes 0 through 3 when shipped from Atmel x = don’ ...
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Erase Sector Protection Register Command In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector Protection Register command. To erase the Sector Protection Register, the CS pin ...
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... Command Program Sector Protection Register Figure 9-3. Program Sector Protection Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB011D 16 , during which time the Status Register will indicate that the device is busy Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Section 9 ...
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Read Sector Protection Register Command To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 32H and 3 dummy bytes must be clocked in via the ...
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... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS SI AT45DB011D 18 Byte 1 3DH Opcode Opcode Opcode Byte 1 ...
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... Reading the Sector Lockdown Register The Sector Lockdown Register can be read to determine which sectors in the memory array are permanently locked down. To read the Sector Lockdown Register, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 35H and 3 dummy bytes must be clocked into the device via the SI pin ...
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... Therefore, the contents of the buffer will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB011D 20 Security Register • • • One-time User Programmable , during which time the Status Register will indicate that the device is busy. If the device P ...
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... Main Memory Page to Buffer Compare A page of data in main memory can be compared to the data in the buffer. To initiate the opera- tion for the DataFlash standard page size, a 1-byte opcode, 60H, must be clocked into the device, followed by three address bytes consisting of 6 don’t care bits, 9 page address bits (PA8 - PA0) that specify the page in the main memory that compared to the buffer, and 9 don’ ...
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... Block Erase, Sector Erase, Chip Erase and Auto Page Rewrite. The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit then the data in the main memory page matches the AT45DB011D 22 Figure 25-1 (page 45) is recommended ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB011D, the four bits are 0011 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
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... RDPD down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB011D 24 time. Once the device has entered the Deep Power-down mode, all instructions EDPD CS SI Each transition represents 8 bits time before the device can receive any commands ...
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... Configuration Register is a user-programmable nonvolatile regis- ter that allows the page size of the main memory to be configured for binary page size (256 bytes) or the DataFlash standard page size (264 bytes). The “power of 2” page size is a One-time Programmable (OTP) register and once the device is configured for “ ...
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... Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. AT45DB011D 26 Bit 3 ...
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... Sector Erase 4. Chip Erase 5. Main Memory Page to Buffer Transfer 6. Main Memory Page to Buffer Compare 7. Buffer to Main Memory Page Program with Built-in Erase 8. Buffer to Main Memory Page Program without Built-in Erase 9. Main Memory Page Program through Buffer 10. Auto Page Rewrite Group C commands consist of: 1 ...
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... Buffer to Main Memory Page Program with Built-in Erase Buffer to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program through Buffer AT45DB011D 28 Read Commands Program and Erase Commands Opcode D2H E8H 03H ...
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... Sector Lockdown Read Sector Lockdown Register Program Security Register Read Security Register Table 15-4. Command Main Memory Page to Buffer Transfer Main Memory Page to Buffer Compare Auto Page Rewrite through Buffer Deep Power-down Resume from Deep Power-down Status Register Read Manufacturer and Device ID Read Table 15-5 ...
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... Page Size = 256 bytes Opcode Opcode 03h 0Bh 50h 53h 58h 60h 77h 7Ch 81h 82h 83h 84h 88h 9Fh B9h ABh D1h D2h D4h D7h E8h Note Don’t Care AT45DB011D 30 Address Byte Address Byte N/A N Address Byte ...
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Table 15-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (264 Bytes) Page Size = 264 bytes Opcode Opcode 03h 0Bh 50h 0 ...
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... The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB011D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in ...
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... IH inputs at CMOS levels MHz mA; OUT MHz mA; OUT MHz mA; OUT MHz mA; OUT CMOS levels CMOS levels I 1 -100 µ AT45DB011D -40°C to 85°C 2.7V to 3.6V Min Typ Max 0 0.7 0.4 - 0.2V Units µA µ µA µ ...
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... P t Page Erase Time (256/264 bytes Block Erase Time (2,048/2,112 bytes Sector Erase Time (32,768/33,792 bytes Chip Erase Time CE t RESET Pulse Width RST t RESET Recovery Time REC AT45DB011D 34 Min Typ Max Units 66 MHz 66 MHz 33 MHz 6.8 ns 6.8 ns 0.1 V/ns 0.1 ...
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Input Test Waveforms and Measurement Levels < (10 20. Output Test Load 21. AC Waveforms Six different timing waveforms are shown on low when CS makes a high-to-low transition, and ...
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... Waveform 1 – SPI Mode 0 Compatible (for Frequencies MHz) CS SCK HIGH IMPEDANCE SO SI 21.2 Waveform 2 – SPI Mode 3 Compatible (for Frequencies MHz) CS SCK HIGH 21.3 Waveform 3 – RapidS Mode SCK HIGH IMPEDANCE SO SI 21.4 Waveform 4 – RapidS Mode SCK HIGH AT45DB011D CSS VALID OUT VALID CSS ...
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Utilizing the RapidS Function To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed ...
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... Command Sequence for Read/Write Operations for Page Size 256 Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB 21.8 Command Sequence for Read/Write Operations for Page Size 264 Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB AT45DB011D 38 CMD 8 bits 8 bits Don’t Care Page Address Bits ...
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... The following block diagram and waveforms illustrate the various write sequences available. PAGE (256/264 BYTES) 22.1 Buffer Write CS SI (INPUT) CMD 22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page (INPUT) Each transition represents 8 bits 3639H–DFLASH–04/09 FLASH MEMORY ARRAY BUFFER TO ...
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... Main Memory Page Read CS SI (INPUT) CMD SO (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer (INPUT) SO (OUTPUT) AT45DB011D 40 FLASH MEMORY ARRAY MAIN MEMORY READ PAGE READ I/O INTERFACE SO ADDRESS FOR BINARY PAGE SIZE A16 A15-A8 ...
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Buffer Read CS SI (INPUT) SO (OUTPUT) Each transition represents 8 bits 24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 3 24.1 Continuous Array Read (Legacy Opcode E8H SCK ...
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... Continuous Array Read (Low Frequency: Opcode 03H SCK MSB HIGH-IMPEDANCE SO 24.4 Main Memory Page Read (Opcode: D2H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.5 Buffer Read (Opcode D4H SCK OPCODE MSB HIGH-IMPEDANCE SO AT45DB011D OPCODE ADDRESS BITS A16- MSB ADDRESS BITS 32 DON'T CARE BITS MSB MSB 6 7 ...
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Buffer Read (Low Frequency: Opcode D1H SCK MSB HIGH-IMPEDANCE SO 24.7 Read Sector Protection Register (Opcode 32H SCK SI 0 MSB HIGH-IMPEDANCE SO 24.8 Read Sector Lockdown Register (Opcode 35H) CS ...
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... Read Security Register (Opcode 77H SCK MSB HIGH-IMPEDANCE SO 24.10 Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition AT45DB011D OPCODE DON'T CARE MSB OPCODE STATUS REGISTER DATA MSB ...
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... This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by- page page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3639H– ...
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... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB011D 46 START ...
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... AT45DB011D-MH-SL955 AT45DB011D-SSH-B AT45DB011D-SSH-T (3) AT45DB011D-SSH-SL954 (4) AT45DB011D-SSH-SL955 AT45DB011D-SH-B AT45DB011D-SH-T (3) AT45DB011D-SH-SL954 (4) AT45DB011D-SH-SL955 Notes: 1. The shipping carrier option is not marked on the devices. 2. Standard parts are shipped with the page size set to 264 bytes. The user is able to configure these parts to a 256-byte page size if desired. 3. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 256 bytes. Parts will have a 954 or SL954 marked on them ...
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... UDFN E Pin TOP VIEW Pin #1 Notch (0.20 R) (Option BOTTOM VIEW L Package Drawing Contact: packagedrawings@atmel.com AT45DB011D 48 SIDE VIEW A1 A 0.45 Option A 1 Pin #1 Chamfer (C 0.35) SYMBOL TITLE 8MA1, 8-pad ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead ...
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JEDEC SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO ...
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... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com AT45DB011D TOP VIEW ...
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... XFR COMP Changed part number ordering code to reflect NiPdAu lead finish. - Changed AT45DB011D-SSU to AT45DB011D-SSH. - Changed AT45DB011D-SU to AT45DB011D-SH. - Changed AT45DB011D-MU to AT45DB011D-MH. Added lead finish details to Ordering Information table. Added Ordering Code Detail. Changed I (Typ) and I (Max), for MHz and 25 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...