AT45DB011-JC Atmel, AT45DB011-JC Datasheet
AT45DB011-JC
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AT45DB011-JC Summary of contents
Page 1
... The AT45DB011 is a 2.7-volt only, serial interface Flash memory suitable for in-system reprogramming. Its 1,081,344 bits of memory are organized as 512 pages of 264 bytes each. In addition to the main memory, the AT45DB011 also contains one SRAM data buffer of 264 bytes. Unlike conventional Flash memories that are ...
Page 2
... AT45DB011 2 To allow for simple in-system reprogrammability, the AT45DB011 does not require high input voltages for pro- gramming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read opera- tions. The AT45DB011 is enabled through the chip select ...
Page 3
... To start a page read, the 8-bit opcode, 52H, is followed by 24 address bits and 32 don’t care bits. In the AT45DB011, the first six address bits are reserved for larger density devices (see Notes on page 9), the next nine address bits (PA8- ...
Page 4
... When a low-to-high transition occurs on the CS pin, the part will first erase the selected page in main memory to all 1s and then program AT45DB011 4 the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the ...
Page 5
... The nine most significant address bits (PA8-PA0) select the page in the main memory where data written, and the next nine address bits (BFA8-BFA0) select the first byte in the buffer to be written. After all address bits are shifted in, the part will take data from the SI pin and store it in the data buffer ...
Page 6
... The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB011, the three bits are 0, 0, and 1. The decimal value of these three binary bits does not equate to the device density; the three bits represent a ...
Page 7
DC Characteristics Symbol Parameter I Standby Current SB I Active Current, Read Operation CC1 I Active Current, Program/Erase CC2 Operation I Input Load Current LI I Output Leakage Current LO V Input Low Voltage IL V Input High Voltage IH ...
Page 8
... Waveform 2 – Inactive Clock Polarity High CS tCSS SCK HIGH AT45DB011 8 times for the SI signal are referenced to the low-to-high transition on the SCK signal. Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3. tWH ...
Page 9
Reset Timing (Inactive Clock Polarity Low Shown) CS SCK RESET HIGH IMPEDANCE SO SI Command Sequence for Read/Write Operations (Except Status Register Read) SI MSB Reserved for larger densities Notes: 1. “r” designates bits reserved for ...
Page 10
... CMD Buffer Write CS SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB011 10 FLASH MEMORY ARRAY BUFFER TO MAIN MEMORY PAGE PROGRAM BUFFER (264 BYTES) BUFFER WRITE I/O INTERFACE SI PA6-0, BFA8 ...
Page 11
... The following block diagram and waveforms illustrate the various read sequences available. PAGE (264 BYTES) Main Memory Page Read CS SI CMD r ···r , PA8-7 SO Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer Buffer Read Each transition represents ...
Page 12
... Detailed Bit-level Read Timing – Inactive Clock Polarity Low Main Memory Page Read CS SCK 1 2 tSU COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB011 HIGH-IMPEDANCE HIGH-IMPEDANCE COMMAND OPCODE DATA OUT MSB 38 39 ...
Page 13
... Detailed Bit-level Read Timing – Inactive Clock Polarity High Main Memory Page Read CS SCK 1 2 tSU COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read CS SCK tSU HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE COMMAND OPCODE DATA OUT MSB DATA OUT MSB ...
Page 14
... Page Read 52H PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 • • • X (64th bit) AT45DB011 14 Main Memory Page Read to Buffer Transfer Opcode 54H 53H PA8 X PA7 X PA6 X PA5 X PA4 ...
Page 15
... PA8 PA8 PA7 PA7 PA6 PA6 PA5 PA5 PA4 PA4 PA3 PA3 PA2 PA2 PA1 PA1 PA0 PA0 Main Memory Page Block Page Program Erase Erase through Buffer Opcode 81H 50H PA8 PA8 PA7 PA7 PA6 PA6 PA5 PA5 PA4 PA4 ...
Page 16
... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB011 16 START provide address ...
Page 17
... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase/program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. Sector Addressing ...
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... Plastic J-leaded Chip Carrier (PLCC) 8S2 8-lead, 0.210" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 14X 14-lead, 0.170" Wide, Plastic Thin Shrink Small Outline Package (TSSOP) AT45DB011 18 Ordering Code AT45DB011-JC AT45DB011-SC AT45DB011-XC AT45DB011-JI AT45DB011-SI AT45DB011-XI Package Type Package Operation Range ...
Page 19
Packaging Information 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE .045(1.14) X 45˚ PIN NO. 1 IDENTIFY .553(14.0) .547(13.9) .032(.813) .595(15.1) .026(.660) .585(14.9) .050(1.27) TYP .300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS ...
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... No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. ...