AT45DB321D-TU Atmel, AT45DB321D-TU Datasheet
AT45DB321D-TU
Specifications of AT45DB321D-TU
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AT45DB321D-TU Summary of contents
Page 1
... MHz. Its 34,603,008 bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream ...
Page 2
... To allow for simple in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
Page 3
... Ground: The ground reference for the power supply. GND should be connected to the system GND ground. 3597H–DFLASH–02/07 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted. CC AT45DB321D [Preliminary] Asserted CC State Type Low Input – ...
Page 4
... RDY/BUSY 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB321D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase operations can be performed at the chip, sector, block or page level ...
Page 5
... The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached during a 3597H–DFLASH–02/07 AT45DB321D [Preliminary] Table 15-1 on page 28 through Table 15-7 on ...
Page 6
... When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred AT45DB321D [Preliminary] 6 specification. The Continuous Array Read bypasses both data buffers and leaves the specification ...
Page 7
... A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). 3597H–DFLASH–02/07 AT45DB321D [Preliminary] specification. The Main Memory Page Read bypasses both data buffers and SCK . The D1H and D3H opcode can be used for lower frequency CAR1 ...
Page 8
... Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of t status register and the RDY/BUSY pin will indicate that the part is busy. AT45DB321D [Preliminary During this time, EP ...
Page 9
... PA7/ PA6/ PA5/ A17 A16 A15 A14 • • • • • • • • • • • • AT45DB321D [Preliminary] PA4/ PA3/ PA2/ PA1/ A13 A12 A11 A10 • • • • • • • • • • • • ...
Page 10
... The erase operation is internally self-timed and should take place in a time of t The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased. AT45DB321D [Preliminary] 10 PA8/ PA7/ PA6/ ...
Page 11
... Status Register. 3597H–DFLASH–02/07 Chip Erase CS Opcode SI Byte 1 Each transition represents 8 bits 1. Refer to the errata regarding Chip Erase on AT45DB321D [Preliminary] Byte 1 Byte 2 Byte 3 C7H 94H 80H Opcode Opcode Opcode Byte 2 ...
Page 12
... Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro- tection is desired and if the WP pin is not used. AT45DB321D [Preliminary] 12 Byte 1 3DH Enable Sector Protection ...
Page 13
... WPE 2 Disable Sector Command Protection Command – Issue Command Issue Command X Not Issued Yet or 2 Issue Command – Issue Command AT45DB321D [Preliminary] , then the content of the Sector CC time) as long as the Enable Sec- WPD 3 Sector Protection Status X Disabled Disabled – Enabled X Enabled ...
Page 14
... Sector Protection Register.: Table 9-2. Sector Number Protected Unprotected Table 9-3. Sectors 0a, 0b Unprotected Protect Sector 0a (Pages 0-7) Protect Sector 0b (Pages 8-127) Protect Sectors 0a (Pages 0-7), 0b (Pages 8-127) Note: AT45DB321D [Preliminary] 14 Sector Protection Register Sector 0 (0a, 0b) 0a (Pages 0-7) Bit (1) 1. The default value for bytes 0 through 63 when shipped from Atmel is 00H don’ ...
Page 15
... Sector Protection Register and before the register can be reprogrammed, then the erroneous program or erase command will not be processed because all sectors would be protected. Command Erase Sector Protection Register Figure 9-2. 3597H–DFLASH–02/07 AT45DB321D [Preliminary] Byte 1 3DH Erase Sector Protection Register CS Opcode Opcode ...
Page 16
... Command Program Sector Protection Register Figure 9-3. Program Sector Protection Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D [Preliminary during which time the Status Register will indicate that the device is busy Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Section 9 ...
Page 17
... Instead, a combination of temporarily unprotecting individual sectors along with dis- abling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded. 3597H–DFLASH–02/ Dummy Byte AT45DB321D [Preliminary] Byte 1 Byte 2 Byte 3 32H xxH xxH Data Byte ...
Page 18
... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D [Preliminary] 18 Byte 1 3DH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Bytes ...
Page 19
... Opcode SO Each transition represents 8 bits 3597H–DFLASH–02/07 Sector 0 (0a, 0b) (Pages 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte Data Byte AT45DB321D [Preliminary] 0 (0a, 0b) See Below 0a 0b (Pages 8-127) Bit 5, 4 Bit ...
Page 20
... Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D [Preliminary] 20 Security Register • • • One-time User Programmable , during which time the Status Register will indicate that the device is busy. If the device P ...
Page 21
... The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. Dur- ing the transfer of a page of data (t monitored to determine whether the transfer has been completed. 3597H–DFLASH–02/07 AT45DB321D [Preliminary Data Byte ...
Page 22
... AT45DB321D [Preliminary the status register and the RDY/BUSY pin will indicate that COMP Figure 25-1 (page 45) is recommended ...
Page 23
... The device density is indicated using bits and 2 of the status register. For the AT45DB321D, the four bits are 1101 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
Page 24
... RDPD down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB321D [Preliminary] 24 time. Once the device has entered the Deep Power-down mode, all instructions EDPD CS SI Each transition represents 8 bits time before the device can receive any commands ...
Page 25
... The fourth byte output will be the Extended Device Information String Length, which will be 00H indicating that no Extended Device Information follows. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional. 3597H–DFLASH–02/07 AT45DB321D [Preliminary] , during which time the Status Register will indicate that the device ...
Page 26
... Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. AT45DB321D [Preliminary] 26 Bit 3 ...
Page 27
... Group C can be executed. The Group B commands using buffer 1 should use Group C commands using buffer 2 and vice versa. Finally, during the internally self- timed portion of a Group D command, only the Status Register Read command should be executed. 3597H–DFLASH–02/07 AT45DB321D [Preliminary] 27 ...
Page 28
... Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB321D [Preliminary] 28 Read Commands Program and Erase Commands Opcode D2H E8H 03H ...
Page 29
... Note: 3597H–DFLASH–02/07 Protection and Security Commands Additional Commands (1) Legacy Commands 1. These legacy commands are not recommended for new designs. AT45DB321D [Preliminary] Opcode 3DH + 2AH + 7FH + A9H 3DH + 2AH + 7FH + 9AH 3DH + 2AH + 7FH + CFH 3DH + 2AH + 7FH + FCH 32H ...
Page 30
... B9h ABh D1h D2h D3h D4h D6h D7h E8h Notes Don’t Care AT45DB321D [Preliminary] 30 Address Byte Address Byte N/A N/A N/A N/A N/A N N/A N Address Byte ...
Page 31
... E8h Notes Page Address Bit B = Byte/Buffer Address Bit 3597H–DFLASH–02/07 Address Byte Address Byte N/A N/A N/A N/A N/A N N/A N Don’t Care AT45DB321D [Preliminary] Address Byte N/A N Additional Don’t Care Bytes B N N/A x N/A x N/A ...
Page 32
... The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB321D [Preliminary During power-up, the internal Power-on Reset circuitry keeps the device in ...
Page 33
... I during a buffer read maximum @ 20 MHz. CC1 2. All inputs are 5 volts tolerant. 3597H–DFLASH–02/07 AT45DB321D [Preliminary] *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...
Page 34
... Page Programming Time (512/528 bytes Page Erase Time (512/528 bytes Block Erase Time (4,096/4,224 bytes Chip Erase Time CE t Sector Erase Time (262,144/270,336 bytes RESET Pulse Width RST t RESET Recovery Time REC AT45DB321D [Preliminary] 34 AT45DB321D Min Typ Max 6.8 6.8 0.1 0 100 ...
Page 35
... MHz) of the RapidS serial case. 3597H–DFLASH–02/07 2.4V AC DRIVING 1.5V LEVELS 0.45V DEVICE UNDER TEST 30 pF period. These timing waveforms are valid over the full frequency range (max- WL AT45DB321D [Preliminary] AC MEASUREMENT LEVEL page 36. Waveform 1 shows the SCK signal being ). Timing waveforms 1 and 2 conform ...
Page 36
... Waveform 1 – SPI Mode 0 Compatible (for frequencies MHz) CS SCK HIGH IMPEDANCE SO SI 21.2 Waveform 2 – SPI Mode 3 Compatible (for frequencies MHz) CS SCK HIGH 21.3 Waveform 3 – RapidS Mode SCK HIGH IMPEDANCE SO SI 21.4 Waveform 4 – RapidS Mode SCK HIGH AT45DB321D [Preliminary CSS VALID OUT VALID CSS ...
Page 37
... Last bit of BYTE-MOSI is clocked into the slave. F. Slave clocks out first bit of BYTE-SO. G. Master clocks in first bit of BYTE-SO. H. Slave clocks out second bit of BYTE-SO. I. Master clocks in last bit of BYTE-SO. 3597H–DFLASH–02/07 ™ Function LSB BYTE-MOSI AT45DB321D [Preliminary MSB BYTE- LSB 37 ...
Page 38
... Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB Don’t Care 21.8 Command Sequence for Read/Write Operations for Page Size 528 Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB AT45DB321D [Preliminary] 38 CMD 8 bits 8 bits 8 bits Page Address Byte/Buffer Address ...
Page 39
... BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 X BFA7-0 X···X, BFA9-8 Starts self-timed erase/program operation BINARY PAGE SIZE A21- DON'T CARE BITS CMD PA12-6 AT45DB321D [Preliminary] BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 (512/528 BYTES) BUFFER 2 WRITE Completes writing into selected buffer n n+1 ...
Page 40
... Main Memory Page Read CS SI (INPUT) CMD SO (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer (INPUT) SO (OUTPUT) AT45DB321D [Preliminary] 40 FLASH MEMORY ARRAY MAIN MEMORY READ PAGE READ I/O INTERFACE SO ADDRESS FOR BINARY PAGE SIZE A15-A8 ...
Page 41
... DON'T CARE + BFA8-BFA0 CMD X X..X, BFA9 ADDRESS BITS 32 DON'T CARE BITS MSB MSB ADDRESS BITS A21 - MSB MSB AT45DB321D [Preliminary] BFA7 Dummy Byte (opcodes D1H and D3H) 1 Dummy Byte (opcodes D4H and D6H DATA BYTE MSB BIT 4095/4223 OF PAGE DON'T CARE DATA BYTE ...
Page 42
... Continuous Array Read (Low Frequency: Opcode 03H SCK MSB HIGH-IMPEDANCE SO 24.4 Main Memory Page Read (Opcode: D2H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.5 Buffer Read (Opcode D4H or D6H SCK OPCODE MSB HIGH-IMPEDANCE SO AT45DB321D [Preliminary OPCODE ADDRESS BITS A21- MSB ADDRESS BITS 32 DON'T CARE BITS MSB MSB 6 7 ...
Page 43
... ADDRESS BITS BINARY PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 STANDARD DATAFLASH PAGE SIZE = OPCODE 14 DON'T CARE + BFA9-BFA0 MSB OPCODE DON'T CARE MSB OPCODE DON'T CARE MSB AT45DB321D [Preliminary DATA BYTE MSB MSB DATA BYTE MSB MSB DATA BYTE MSB MSB 43 ...
Page 44
... Read Security Register (Opcode 77H SCK MSB HIGH-IMPEDANCE SO 24.10 Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition AT45DB321D [Preliminary OPCODE DON'T CARE MSB OPCODE STATUS REGISTER DATA ...
Page 45
... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3597H–DFLASH–02/07 START provide address (82H, 85H) END AT45DB321D [Preliminary] and data BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) ...
Page 46
... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB321D [Preliminary] 46 START ...
Page 47
... Plastic Gull Wing Small Outline Package (EIAJ SOIC) 28T 28-lead 13.4 mm, Plastic Thin Small Outline Package, Type I (TSOP) 3597H–DFLASH–02/07 AT45DB321D [Preliminary] Ordering Code AT45DB321D-MU AT45DB321D-SU AT45DB321D-TU AT45DB321D-MWU (1) Ordering Code AT45DB321D-CNU Package Type Package Operation Range 8M1-A ...
Page 48
... All dimensions and tolerance conform to ASME Y 14.5M, 1994. 2. The surface finish of the package shall be EDM Charmille #24-27. 3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2 4. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321D [Preliminary Top View Side View Pin1 Pad Corner L1 ...
Page 49
... San Jose, CA 95131 R 3597H–DFLASH–02/ Pin 1 ID TOP VIEW Pin #1 Notch (0. TITLE 8M1-A, 8-lead 1.00 mm Body, Very Thin Dual Flat Package No Lead (MLF) AT45DB321D [Preliminary] SIDE VIEW A3 A1 0.08 C COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A – 0.85 1.00 A1 – – ...
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... MLF D Pin TOP VIEW D1 Pin # BOTTOM VIEW 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321D [Preliminary Option A Pin #1 Chamfer (C 0.30) Option B e Pin #1 K Notch (0.20 R) TITLE 8MW, 8-pad 1.0 mm Body, Very Thin Dual Flat Package No Lead (MLF) SIDE VIEW ...
Page 51
... San Jose, CA 95131 R 3597H–DFLASH–02/ TOP VIEW TOP VIEW SIDE VIEW SIDE VIEW TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) AT45DB321D [Preliminary θ θ END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 1.70 2.16 A1 0.05 ...
Page 52
... E Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321D [Preliminary] 52 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) 0º ...
Page 53
... Changed the Product Version Code to 00001. Corrected typographical errors. Added errata regarding Chip Erase. Added AT45DB321D-SU to ordering information and corresponding 8S2 package. Removed “not recommended for new designs” note from ordering information for 8MW package. Added AT45DB321D-CNU to ordering information and corresponding 8CN3 package. Removed “ ...
Page 54
... Use Block Erase (opcode 50H alternative. The Block Erase function is not affected by the Chip Erase issue. 29.1.3 Resolution The Chip Erase feature may be fixed with a new revision of the device. Please contact Atmel for the estimated availability of devices with the fix. AT45DB321D [Preliminary] 54 3597H–DFLASH–02/07 ...
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