EVAL-AD5449SDZ Analog Devices, EVAL-AD5449SDZ Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD5449SDZ
• Description: Data Conversion IC Development Tools evaluation board i.c.
• Manufacturer: Analog Devices
• Type: DACr

Specifications of EVAL-AD5449SDZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD5449
• Interface Type: USB
• Operating Supply Voltage: 5 V, +/- 12 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 1
• For Use With: EVAL-SDP-CB1Z

Evaluation Board User Guide
Table 1. Control Functions
Control Function
Load and Update DAC A
Initiate Readback on DAC A
Load Input Register of DAC A
Load and Update DAC B
Initiate Readback on DAC B
Load Input Register of DAC B
Update Both DACs
Load Input Registers of DAC A
and DAC B
Clear Both Outputs to Zero
Scale
Clear Both Outputs to
Midscale
Table 2.
Control Register
SDO Configuration
Daisy-Chain Mode
Hardware Clear
Active SCLK Edge
Load Control Word
Description
Loads the DAC A register with the entered data-word and updates the DAC A output, irrespective of the
state of /LDAC.
Reads the contents of the DAC A register and displays the value on screen.
Loads the DAC A input register with the entered data-word. The DAC A output is updated only if /LDAC
is low.
Loads the DAC B register with entered data-word and updates the DAC B output, irrespective of the state
of /LDAC.
Reads the contents of the DAC B register and displays the value on screen.
Loads the DAC B input register with the entered data-word. The DAC B output is updated only if /LDAC
is low.
Updates both DAC outputs with the entered data-word, irrespective of the state of /LDAC.
Loads the input registers of both DACs with the entered data-word. Both outputs are updated only if
/LDAC is low.
Loads both DACs and updates their outputs with zero-scale code, irrespective of the state of /LDAC.
Loads both DACs and updates their outputs with midscale code, irrespective of the state of /LDAC.
Description
The SDO bits enable you to control the SDO output driver strength, disable the SDO output, or configure
the SDO as an open-drain driver. The strength of the SDO driver affects timing. A stronger SDO output
driver allows a faster clock cycle to be used.
Enables or disables daisy-chain functionality.
Sets the value to which the outputs are cleared on the falling edge of the CLR signal. The value can be
either zero scale or midscale.
Selects the edge of SCLK on which data is clocked into the input register. Data is clocked out from SDO on
the opposite edge.
Loads control register mode.
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