IS45S16400E-7TLA2-TR ISSI, Integrated Silicon Solution Inc, IS45S16400E-7TLA2-TR Datasheet
IS45S16400E-7TLA2-TR
Specifications of IS45S16400E-7TLA2-TR
Related parts for IS45S16400E-7TLA2-TR
IS45S16400E-7TLA2-TR Summary of contents
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... Integrated Silicon Solution, Inc. — www.issi.com Rev. F 01/13/2010 JANUARY 2010 OVERVIEW ISSI 's 64Mb Synchronous DRAM IS45S16400E is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance.ThesynchronousDRAMsachievehigh-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS ...
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... IS45S16400E GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode ...
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... IS45S16400E PIN FUNCTIONS Symbol TSOP Pin No. Type A0-A11 Input Pin 22, 35 BA0, BA1 20, 21 Input Pin 17 Input Pin CAS CKE 37 Input Pin CLK 38 Input Pin 19 Input Pin CS DQ0 10, DQ Pin DQ15 11,13, 42, 44, 45, 47, 48, 50, 51, 53 LDQM, 15, 39 Input Pin UDQM ...
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... IS45S16400E READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A7 provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst ...
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... IS45S16400E LOAD MODE REGISTER During the LOAD MODE REGISTER command the mode register is loaded from A0-A11. This command can only be issued when all banks are idle. ACTIVE COMMAND When the ACTIVE COMMAND is activated, BA0, BA1 inputs selects a bank to be accessed, and the address inputs on A0-A11 selects the row ...
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... IS45S16400E TRUTH TABLE – COMMANDS AND DQM OPERATION FUNCTION COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank/column, start READ burst) WRITE (Select bank/column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH ...
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... IS45S16400E TRUTH TABLE – CKE (1-4) CURRENT STATE COMMANDn Power-Down X Self Refresh X Clock Suspend X Power-Down COMMAND INHIBIT or NOP (5) Self Refresh (6) COMMAND INHIBIT or NOP Clock Suspend X (7) All Banks Idle COMMAND INHIBIT or NOP All Banks Idle AUTO REFRESH Reading or Writing VALID See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n NOTES: 1. CKEn is the logic state of CKE at clock edge n ...
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... IS45S16400E 3. Current state definitions: Idle: The bank has been precharged, and t Row Active: A row in the bank has been activated, and t accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi- nated. ...
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... IS45S16400E TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m CURRENT STATE COMMAND (ACTION) Any COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Idle Any Command Otherwise Allowed to Bank m Row ACTIVE (Select and activate row) Activating, READ (Select column and start READ burst) ...
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... IS45S16400E 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter- rupted by bank m’s burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Consecutive READ Bursts) ...
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... IS45S16400E ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD max V Maximum Supply Voltage for Output Buffer DDq max V Input Voltage iN V Output Voltage out P Allowable Power Dissipation D max I output Shorted Current cs T operating Temperature opr T Storage Temperature stg DC RECOMMENDED OPERATING CONDITIONS ...
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... IS45S16400E DC ELECTRICAL CHARACTERISTICS Symbol Parameter i Input Leakage Current il i Output Leakage Current ol V Output High Voltage Level oh V Output Low Voltage Level ol i Operating Current (1,2) cc1 i Precharge Standby Current cc2p I (In Power-Down Mode) cc2ps i Precharge Standby Current (3) cc2N I (In Non Power-Down Mode) ...
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... IS45S16400E AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time ck3 t ck2 t Access Time From CLK (4,6) ac3 t ac2 t CLK HIGH Level Width chi t CLK LOW Level Width cl t Output Data Hold Time (6) oh3 t oh2 t Output LOW Impedance Time lz t Output HIGH Impedance Time ...
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... IS45S16400E OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t READ/WRITE command to READ/WRITE command ccD t CKE to clock disable or power-down entry mode ckeD t CKE to clock enable or power-down exit setup mode peD t DQM to input data delay DqD t DQM to data mask during WRITEs ...
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... IS45S16400E FUNCTIONAL DESCRIPTION The 64Mb SDRAMs (1 Meg banks) are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; ...
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... IS45S16400E REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power ...
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... IS45S16400E Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst ...
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... IS45S16400E CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...
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... IS45S16400E OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...
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... IS45S16400E READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...
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... IS45S16400E diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t is met. Note that part of the row precharge time is rp hidden during the access of the last data element(s) ...
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... IS45S16400E Consecutive READ Bursts T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP READ BANK, COL n+1 D OUT OUT NOP NOP READ BANK, COL n+1 OUT OUT Integrated Silicon Solution, Inc. — www.issi.com ...
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... IS45S16400E Random READ Accesses T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 01/13/2010 READ READ READ BANK, BANK, BANK, COL b COL m COL OUT OUT CAS Latency - 2 T1 ...
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... IS45S16400E RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL NOP NOP NOP NOP n+1 D n+2 OUT OUT OUT NOP NOP NOP OUT CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com ...
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... IS45S16400E READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 01/13/2010 NOP NOP NOP PRECHARGE cycle BANK (a or all n+1 ...
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... IS45S16400E READ Burst Termination T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - BURST NOP NOP NOP TERMINATE n+1 D OUT OUT BURST NOP NOP TERMINATE cycles n+1 OUT OUT Integrated Silicon Solution, Inc. — www.issi.com ...
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... IS45S16400E WRITEs WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE Command CLK HIGH CKE CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9, A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...
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... IS45S16400E WRITE Burst CLK COMMAND ADDRESS WRITE to WRITE COMMAND Random WRITE Cycles COMMAND ADDRESS WRITE NOP NOP BANK, COL n CLK WRITE NOP BANK, ADDRESS COL n DON'T CARE CLK WRITE WRITE WRITE BANK, BANK, BANK, COL n COL b COL Integrated Silicon Solution, Inc. — www.issi.com ...
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... IS45S16400E WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL Integrated Silicon Solution, Inc. — www.issi.com Rev. F 01/13/2010 NOP READ NOP BANK, COL b D n+1 IN CAS Latency - NOP NOP ACTIVE PRECHARGE BANK ...
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... IS45S16400E WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS NOP NOP NOP PRECHARGE BANK (a or all n+1 IN CAS Latency - CLK BURST WRITE TERMINATE BANK, (ADDRESS) COL DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com ...
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... IS45S16400E PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks.The bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE rp command is issued. Input A10 determines whether one or ...
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... IS45S16400E CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ...
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... IS45S16400E BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access ...
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... IS45S16400E WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after t is met, where t begins when the READ to bank registered ...
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... IS45S16400E INITIALIzE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µs Min. ...
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... IS45S16400E POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks power-down mode ...
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... IS45S16400E CLOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/ DQML, DQMH A0-A9, A11 COLUMN m ( A10 BA0, BA1 BANK DQ Notes: 1. CAS latency = 3, burst length = and A = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev ...
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... IS45S16400E AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z t CAS latency = Auto NOP Refresh Integrated Silicon Solution, Inc. — www.issi.com Tn+1 To+1 ...
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... IS45S16400E SELF-REFRESH CYCLE CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High Precharge all Enter self active banks refresh mode CAS latency = 2, 3 Note: 1. Self-Refresh Mode is not supported for A2 grade with T Integrated Silicon Solution, Inc. — ...
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... IS45S16400E READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = and A = " ...
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... IS45S16400E READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = and A = " ...
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... IS45S16400E SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = 1 2 ...
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... IS45S16400E SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = and A = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev ...
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... IS45S16400E ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1. CAS latency = 2, burst length = 4 2 ...
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... IS45S16400E READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 BANK BANK DQ t RCD Notes: 1. CAS latency = 2, burst length = full page and A = "Don't Care" ...
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... IS45S16400E READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD Notes: 1. CAS latency = 2, burst length = and A = " ...
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... IS45S16400E WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" ...
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... IS45S16400E WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" WRITE NOP ...
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... IS45S16400E SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" ...
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... IS45S16400E SINGLE WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND (3) ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" (3) (3) NOP NOP WRITE ...
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... IS45S16400E ALTERNATING BANK WRITE ACCESS CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK 0 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1. burst length = 4 2 ...
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... IS45S16400E WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1. burst length = full page and A = "Don't Care" WRITE NOP NOP t t CMS ...
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... IS45S16400E WRITE - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1. burst length = and A = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev. F 01/13/2010 ...
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... IS45S16400E-7TLA1 Automotive Range A2: -40°C to +105°C Frequency Speed (ns) Order Part No. 143 MHz 7 IS45S16400E-7TLA2 Notes: 1. Contact Product Marketing for leaded parts support. 2. Part numbers with "L" or "N" are leadfree, and RoHs compliant 3.3V DD Package 54-pin TSOPII, Alloy42 leadframe plated with matte Sn ...
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... IS45S16400E Integrated Silicon Solution, Inc. — www.issi.com Rev. F 01/13/2010 55 ...