M25P10-AVMN6P NUMONYX, M25P10-AVMN6P Datasheet
M25P10-AVMN6P
Specifications of M25P10-AVMN6P
497-3591
Available stocks
Related parts for M25P10-AVMN6P
M25P10-AVMN6P Summary of contents
Page 1
... Deep Power-down mode 1 μA (typical) Electronic signatures – JEDEC standard two-byte signature (2011h) – RES instruction, one-byte signature (10h), for backward compatibility More than 20 years’ data retention Packages – RoHS compliant December 2008 SO8 (MN) 150 mil width VFQFPN8 (MP) (MLP8) UFDFPN8 (MB Rev 12 M25P10-A 1/51 1 www.numonyx.com ...
Page 2
... Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . .11 4.4 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . .11 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR) ...
Page 3
Read Data Bytes (READ ...
Page 4
... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 10. Operating conditions Table 11 ...
Page 5
... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO, VFQFPN and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Hold condition activation Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write Enable (WREN) instruction sequence Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9 ...
Page 6
... Description The M25P10 Mbit (128 Kbit x 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes wide ...
Page 7
Figure 2. SO, VFQFPN and UFDFPN8 connections There is an exposed die paddle on the underside of the MLP8 packages. This is pulled, internally and must not be allowed to be connected to any other ...
Page 8
... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). ...
Page 9
... Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P10-A is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at ...
Page 10
Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 μs. Figure 4. SPI modes supported CPOL CPHA ...
Page 11
... Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction ...
Page 12
... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P10-A features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification. ...
Page 13
... To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. Memory content Protected area All sectors Lower three-quarters (three sectors ...
Page 14
Figure 5. Hold condition activation C HOLD 14/51 Hold condition (standard use) (non-standard use) Hold condition AI02029D ...
Page 15
... Memory organization The memory is organized as: 131,072 bytes (8 bits each) 4 sectors (256 Kbits, 32768 bytes each) 512 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is sector or bulk erasable (bits are erased from but not page erasable. ...
Page 16
... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. ...
Page 17
Table 4. Instruction set Instruction WREN Write Enable WRDI Write Disable (1) RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes Read Data Bytes at Higher FAST_READ Speed PP Page Program SE Sector Erase ...
Page 18
Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is ...
Page 19
... The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (11h) ...
Page 20
... The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is in progress. ...
Page 21
Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence ...
Page 22
... Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification ...
Page 23
... Protected area Protected against Page Program, Sector Erase and Bulk Erase Protected against Page Program, Sector Erase and Bulk Erase 0 1 AI02282D Memory content Unprotected (1) (1) area Ready to accept Page Program and Sector Erase instructions Ready to accept Page Program and Sector Erase ...
Page 24
... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
Page 25
... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
Page 26
... Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
Page 27
Figure 14. Page Program (PP) instruction sequence Instruction Data byte ...
Page 28
Sector Erase (SE) The Sector Erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
Page 29
Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...
Page 30
Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as a software protection mechanism, while the device ...
Page 31
... Deep Power-down mode. The instruction can also be used to read, on Serial Data output (Q), the 8-bit electronic signature, whose value for the M25P10-A is 10h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Electronic Signature (RES) instruction always provides access to the 8-bit electronic signature of the device, and can be applied even if the Deep Power-down mode has not been entered ...
Page 32
... Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit electronic signature, for the M25P10-A, is 10h. Figure 19. Release from Deep Power-down (RES) instruction sequence High Impedance Q 32/ dummy bytes ...
Page 33
Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at power-up, and then for a further delay ...
Page 34
Figure 20. Power-up timing (max (min) Reset state of the device V WI Table 8. Power-up timing and V Symbol ( (min low VSL CC (1) t Time delay to ...
Page 35
... CC V Electrostatic discharge voltage (Human Body model) ESD 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx RoHS compliant 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω). Table 9: Absolute maximum ratings ...
Page 36
DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the ...
Page 37
Table 13. Capacitance Symbol Parameter C Output capacitance (Q) OUT C Input capacitance (other pins Sampled only, not 100% tested Table 14. DC characteristics (device grade 6) Symbol Parameter I Input Leakage current LI I Output ...
Page 38
Table 15. DC characteristics (device grade 3) Symbol Parameter I Input Leakage current LI I Output Leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating ...
Page 39
Table 17. Instruction times (device grade 3) Test conditions specified in Symbol Alt. Parameter t Write Status Register cycle time W Page Program cycle time (256 bytes) ( Page Program cycle time (n bytes) t Sector Erase cycle ...
Page 40
Table 18. AC characteristics (25 MHz operation, device grade Symbol Alt. Clock frequency for the following f f instructions: FAST_READ, PP, SE, BE, DP RES, WREN, WRDI, RDSR, WRSR f Clock frequency for READ instructions ...
Page 41
Table 19. AC characteristics (40 MHz operation, device grade 6) 40 MHz available for products marked since week 20 of 2004, only Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PP, SE, BE, ...
Page 42
Table 20. AC characteristics (50 MHz operation, device grade 6) 50 MHz available only in products with process technology code Y Symbol Alt. Clock frequency f f FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI RDID, RDSR, WRSR ...
Page 43
Figure 22. Serial input timing S tCHSL tSLCH C tDVCH MSB IN D High Impedance Q Figure 23. Write Protect Setup and Hold timing during WRSR when SRWD=1 W tWHSL High Impedance Q tCHSH tCHDX tCLCH LSB ...
Page 44
Figure 24. Hold timing HOLD Figure 25. Output timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN 44/51 tHLCH tCHHL tCHHH tHLQZ tCH tCLQV tCL tQLQH tQHQL tHHCH tHHQX AI02032 tSHQZ LSB OUT AI01449e ...
Page 45
... Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 26. SO8 narrow – ...
Page 46
Figure 27. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, package outline Drawing is not to scale. 2. The circle in the top view of the package indicates the position of ...
Page 47
Figure 28. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead package outline Drawing is not to scale. Table 23. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual ...
Page 48
... For more information on how to identify products by the process identification letter, please refer to AN1995: Serial Flash memory device marking. 4. Only available for grade 6 devices. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 48/51 M25P10-A ( ...
Page 49
... All packages are RoHS compliant. Grade 3 information added (see Table 10, Table 11, Table 15, Figure 3: Bus master and memory devices on the SPI bus Note 2 added. Table 11: Data retention and endurance 40MHz frequency condition modified for I 6 characteristics (device grade Table 14: DC characteristics (device grade 6) ...
Page 50
... Table 24: Ordering information Code of the UFDFPN8 package modified. Small text changes. Applied Numonyx branding. Added the following to Operating Voltage section of information scheme: – Vcc = 2.7 to 3.6 V for /X parts – Vcc = 2.3 to 3.6 V for /Y parts Changes ...
Page 51
... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...