M25P10-AVMN6P NUMONYX, M25P10-AVMN6P Datasheet - Page 25

• Manufacturer Part Number: M25P10-AVMN6P
• Description: IC FLASH 1MBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P10-AVMN6P

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 128K X 8bit
• Access Time: 1.4ms
• Memory Ic Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To + 85°C
• Case Style: SOIC
• Base Number: 25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3591; 497-3591

6.7
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit
being shifted out, at a maximum frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
1. Address bits A23 to A17 are Don’t care.
S
C
D
Q
S
C
D
Q
and data-out sequence
7
32 33 34
0
6
1
High Impedance
Dummy byte
5
2
Instruction
4
35
3
3
36 37 38 39 40 41 42 43 44 45 46
4
2
5
1
6
0
7
MSB
23
7
8
Figure
22 21
6
9 10
24-bit address
DATA OUT 1
5
C
13.
4
, during the falling edge of Serial Clock (C).
3
3
28 29 30 31
2
2
1
1
0
0
47
MSB
7
6
DATA OUT 2
5
4
3
2
1
0
MSB
AI04006
7
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