M25P40-VMN3PB NUMONYX, M25P40-VMN3PB Datasheet - Page 10

• Manufacturer Part Number: M25P40-VMN3PB
• Description: IC FLASH 4MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P40-VMN3PB

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: SO-8
• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 15ns
• Interface Type: Serial (SPI)
• Address Bus: 1b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 125C
• Package Type: SO N
• Program/erase Volt (typ): 2.3 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Automotive
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in Stand-by mode and not transferring data:
Figure 3.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3: Bus Master and memory devices on the SPI bus
devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only
one device drives the Serial Data output (Q) line at a time, the other devices are high
impedance. Resistors R (represented in
the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter
a state where all inputs/outputs are in high impedance at the same time (for example, when
the Bus Master is reset), the clock line (C) must be connected to an external pull-down
resistor so that, when all inputs/outputs become high impedance, the S line is pulled High
while the C line is pulled Low (thus ensuring that S and C do not become High at the same
time, and so, that the t
that the time constant R*C
time during which the Bus Master leaves the SPI bus in high impedance.
SPI Interface with
CS3
(CPOL, CPHA) =
SPI Bus Master
(0, 0) or (1, 1)
CPOL=0, CPHA=0
CPOL=1, CPHA=1
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
CS2 CS1
Bus Master and memory devices on the SPI bus
SDO
SDI
SCK
R
SHCH
R
p
requirement is met). The typical value of R is 100K Ω, assuming
(C
C Q D
S
p
SPI Memory
= parasitic capacitance of the bus line) is shorter than the
Device
W
V
CC
HOLD
Figure
V
R
SS
3) ensure that the M25P40 is not selected if
C Q D
S
Figure
SPI Memory
Device
W
shows an example of three
4, is the clock polarity when the
V
HOLD
CC
V
R
SS
C Q D
S
SPI Memory
Device
W
V
CC
HOLD
AI12836b
V
SS
V
V
CC
SS