M25P40-VMN3PB NUMONYX, M25P40-VMN3PB Datasheet - Page 22

• Manufacturer Part Number: M25P40-VMN3PB
• Description: IC FLASH 4MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P40-VMN3PB

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: SO-8
• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 15ns
• Interface Type: Serial (SPI)
• Address Bus: 1b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 125C
• Package Type: SO N
• Program/erase Volt (typ): 2.3 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Automotive
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4
6.4.1
6.4.2
22/61
Figure 9.
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in
Table 6.
The status and control bits of the Status Register are as follows:
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
Status Register Write Protect
S
C
D
Q
SRWD
b7
Read Identification (RDID) instruction sequence and data-out sequence
Status Register format
0
High Impedance
1
0
2
Instruction
3
4
5
0
6
7
MSB
Manufacturer Identification
8
BP2
9 10 11 12 13 14 15
BP1
Block Protect bits
MSB
15 14 13
16 17 18
Write Enable Latch bit
BP0
Device Identification
Figure
3
28 29 30 31
WEL
Write In Progress bit
2
10.
1
0
AI06809b
WIP
b0