IDT71V016SA10PHG IDT, Integrated Device Technology Inc, IDT71V016SA10PHG Datasheet - Page 7

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IDT71V016SA10PHG

Manufacturer Part Number
IDT71V016SA10PHG
Description
IC SRAM 1MBIT 10NS 44TSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
-r
Datasheet

Specifications of IDT71V016SA10PHG

Format - Memory
RAM
Memory Type
SRAM
Memory Size
1M (64K x 16)
Speed
10ns
Interface
Parallel
Voltage - Supply
3.15 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
44-TSOP II
Density
1Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
SDR
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
16b
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
160mA
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Word Size
16b
Number Of Words
64K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
71V016SA10PHG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT71V016SA10PHG
Manufacturer:
TI
Quantity:
8 769
Part Number:
IDT71V016SA10PHG
Manufacturer:
IDT
Quantity:
20 000
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
DATA
ADDRESS
ADDRESS
DATA
on the bus for the required t
BHE, BLE
BHE, BLE
DATA
DATA
OUT
OUT
WE
WE
CS
CS
IN
IN
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t
t
AS
t
AS
t
t
AW
AW
t
WP
CW
t
t
must be greater than or equal to t
WP
WP
(2)
t
t
t
WC
BW
WC
6.42
7
t
CW
(2)
t
BW
DATA
t
DATA
t
DW
DW
IN
IN
Commercial and Industrial Temperature Ranges
VALID
VALID
WHZ
+ t
DW
t
t
DH
DH
t
WR
t
to allow the I/O drivers to turn off and data to be placed
WR
(1,4)
3834 drw 09
3834 drw 10
(1,4)
WP
.

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