IDT71V3577S75BG IDT, Integrated Device Technology Inc, IDT71V3577S75BG Datasheet - Page 2

• Manufacturer Part Number: IDT71V3577S75BG
• Description: IC SRAM 4MBIT 75NS 119BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71V3577S75BG

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 36)
• Speed: 75ns
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 71V3577S75BG

Pin Definitions
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
I/O
BW
I/O
Symbol
A
ADSC
ADSP
TRST
BWE
V
ADV
P1
LBO
TMS
TDO
CLK
TCK
CS
CS
GW
V
V
0
OE
TDI
CE
0
NC
1
ZZ
DDQ
-A
-I/O
DD
SS
-BW
-I/O
0
1
17
31
P4
4
Linear Burst Order
(Cache Controller)
Byte Write Enable
Test ModeSelect
Data Input/Output
Address Status
Address Status
Test DataOutput
Address Inputs
Test Data Input
Burst Address
Individual Byte
Power Supply
Power Supply
Write Enables
Output Enable
Pin Function
Chip Select 0
Chip Select 1
Chip Enable
Global Write
Sleep Mode
JTAG Reset
No Connect
(Processor)
Test Clock
(Optional)
Advance
Ground
Enable
Clock
(1)
N/A
N/A
N/A
N/A
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK
and ADSC Low or ADSP Low and CE Low.
Synchronous Addre ss Status from Cache Controller. ADSC is an active LOW input that is used to load the
address registers with new addresses.
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
registers with new addresses. ADSP is gated by CE.
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter,
controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not
incremented; that is, there is no address advance.
Synchronous byte write enable gates the byte write inputs BW
blocked and only GW can initiate a write cycle.
Synchronous byte write enables. BW
Synchronous chip enable. CE is used with CS
Synchronous active HIGH chip select. CS
Synchronous active LOW chip select. CS
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
Synchronous data inp ut/output (I/O) pins. The data input path is registered, triggered by the rising edge of
CLK. The data output path is flow-through (no output register).
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP co ntroller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
Serial output of registers placed be tween TDI and TDO. This output is active depending on the state of the
Optional Asynchronous JTAG rese t. Can be used to reset the TAP contro ller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull
down.
Ground.
NC pins are not electrically connected to the device.
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
write causes all outputs to be disabled.
This is the clock input. All timing references for the device are made with respect to this input.
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is selected.
When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state
while the device is operating.
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TAP controller.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3577/79 to
3.3V core power supply.
3.3V I/O Supply.
6.42
2
1
controls I/O
1
0
is used with CE and CS
is used with CE and CS
0
Commercial and Industrial Temperature Ranges
and CS
Description
0-7
, I/O
1
P1
to enable the IDT71V3577/79. CE also gates ADSP.
, BW
1
-BW
2
controls I/O
0
1
4
. If BWE is LOW at the rising edge of CLK
to enable the chip.
to enable the chip.
8-15
, I/O
P2
, etc. Any active byte
5280 tbl 02