IDT7024S55J8 IDT, Integrated Device Technology Inc, IDT7024S55J8 Datasheet - Page 20

• Manufacturer Part Number: IDT7024S55J8
• Description: IC SRAM 64KBIT 55NS 84PLCC
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT7024S55J8

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 64K (4K x 16)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7024S55J8

read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
2K blocks of Dual-Port RAM with each other.
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the Dual-
Port RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
The blocks do not have to be any particular size and can even be
Semaphores are a useful form of arbitration in systems like disk
SEMAPHORE
WRITE
L PORT
D
REQUEST FLIP FLOP
0
READ
SEMAPHORE
D
Figure 4. IDT7024 Semaphore Logic
Q
6.42
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state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
Semaphores are also useful in applications where no memory “WAIT”
Another application is in the area of complex data structures. In this
REQUEST FLIP FLOP
Military, Industrial and Commercial Temperature Ranges
SEMAPHORE
Q
D
SEMAPHORE
READ
R PORT
D
WRITE
2740 drw 20
0
,