24LC32/P Microchip Technology, 24LC32/P Datasheet - Page 8

• Manufacturer Part Number: 24LC32/P
• Description: IC EEPROM 32KBIT 400KHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 24LC32/P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 32K (4K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6.0 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

24LC32
6.3
The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 256K
bits by adding up to eight 24LC32's on the same bus.
In this case, software can use A0 of the control byte as
address bit A12, A1 as address bit A13, and A2 as
address bit A14.
6.4
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC32 transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24LC32 to transmit the
next sequentially addressed 8 bit word (Figure 6-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition.
FIGURE 6-2:
FIGURE 6-3:
DS21072G-page 8
SDA LINE
ACTIVITY:
BUS
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
Contiguous Addressing Across
Multiple Devices
Sequential Read
S
A
R
S
T
T
CONTROL
RANDOM READ
BYTE
SEQUENTIAL READ
CONTROL
BYTE
A
C
K
A
C
K
0 0 0
ADDRESS (1)
DATA n
WORD
0
A
C
K
C
A
K
DATA n + 1
ADDRESS (0)
WORD
To provide sequential reads the 24LC32 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The address pointer, however,
will not roll over from address 07FF to address 0000. It
will roll from 07FF to unused memory space.
6.5
The SCL and SDA inputs have filter circuits which sup-
press noise spikes to ensure proper device operation
even on a noisy bus. All I/O lines incorporate Schmitt
triggers for 400 kHz (Fast Mode) compatibility.
A
C
K
A
C
K
DATA n + 2
R
Noise Protection
S
T
A
T
S
CONTROL
BYTE
A
C
K
2004 Microchip Technology Inc.
C
A
K
DATA n + X
DATA n
N
O
A
C
K
S
T
O
P
P
O
N
C
A
K
O
S
T
P
P