AT45DB161B-TI-2.5 Atmel, AT45DB161B-TI-2.5 Datasheet
AT45DB161B-TI-2.5
Specifications of AT45DB161B-TI-2.5
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AT45DB161B-TI-2.5 Summary of contents
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... Inputs: SI, SCK, CS, RESET and WP Pins • Commercial and Industrial Temperature Ranges • Green (Pb/Halide-free) Packaging Options Description The AT45DB161B is a 2.5-volt or 2.7-volt only, serial interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage Pin Configurations Pin Name Function CS ...
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... The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB161B is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
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... Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock AT45DB161B PAGE ARCHITECTURE 8 Pages PAGE 0 ...
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... AT45DB161B 4 cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked into the device followed by 24 address bits and 32 don’t care bits. The first two bits of the 24-bit address sequence are reserved for upward and downward compatibility to larger and smaller density devices (see Notes under “ ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB161B, the four bits are and 1. The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of sixteen dif- ferent density configurations ...
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... AT45DB161B 6 BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or 89H for buffer 2, must be followed by the two reserved bits, 12 address bits (PA11 - PA0) that specify the page in the main memory to be written, and ten additional don’ ...
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... The operation is inter- nally self-timed and should take place in a maximum time of t status register will indicate that the part is busy. AT45DB161B . During EP ), the status XFR ...
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... Operation Mode Summary Pin Descriptions AT45DB161B sector is programmed or reprogrammed sequentially page-by-page, then the pro- gramming algorithm shown in Figure 1 on page 26 is recommended. Otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in Figure 2 on page 27 is recommended. Each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector ...
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... CS pin will be required to start a valid instruc- tion. The SPI mode will be automatically selected on every falling edge sampling the inactive clock state. After power is applied and V datasheet value, the system should wait 20 ms before an operational mode is started. AT45DB161B is at the minimum CC 9 ...
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... Auto Page Rewrite through Buffer 2 Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3). AT45DB161B 10 SCK Mode Inactive Clock Polarity Low or High ...
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... D4H D6H D7H E8H Note Reserved Bit P = Page Address Bit B = Byte/Buffer Address Bit x = Don’t Care 2224I–DFLSH–10/04 Address Byte Address Byte N/A N N/A N AT45DB161B Address Byte N N Additional Don’t Care Bytes Required Bytes Byte x x N/A ...
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... V Output High Voltage OH Note during a buffer read is 20mA maximum. cc1 AT45DB161B 12 *NOTICE: + 0.6V CC AT45DB161B (2.5V Version) Com. Ind. 2. the minimum specified datasheet value, the system should wait 20 ms before an opera- CC Condition CS, RESET all inputs CC at CMOS levels MHz mA; ...
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... Page Erase and Programming Time EP t Page Programming Time P t Page Erase Time PE t Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC 2224I–DFLSH–10/04 AT45DB161B AT45DB161B (2.5V Version) AT45DB161B Min Max Min 250 250 250 250 250 250 200 ...
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... Output Test Load AC Waveforms Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0 CS SCK HIGH IMPEDANCE SO SI Waveform 2 – Inactive Clock Polarity High and SPI Mode CSS SCK HIGH AT45DB161B 14 2.4V AC 2.0 DRIVING 0.8 LEVELS 0.45V < (10 DEVICE UNDER ...
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... For densities larger than 16M bits, the “r” bits become the most significant Page Address bit for the appropriate density. 2224I–DFLSH–10/04 SI CMD 8 bits 8 bits Page Address (PA11-PA0) (BA9-BA0/BFA9-BFA0) AT45DB161B t t REC CSS t RST HIGH IMPEDANCE 8 bits LSB Byte/Buffer Address ...
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... SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB161B 16 The following block diagram and waveforms illustrate the various write sequences available. FLASH MEMORY ARRAY MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 ...
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... FLASH MEMORY ARRAY MAIN MEMORY PAGE READ I/O INTERFACE SO BA7-0 X PA5-0, BA9-8 Starts reading page data into buffer CMD PA11-6 PA5-0, XX CMD X X···X, BFA9-8 BFA7-0 AT45DB161B MAIN MEMORY PAGE TO BUFFER 2 BUFFER 2 (528 BYTES) BUFFER 2 READ n 1st byte read ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity Low Continuous Array Read (Opcode: 68H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE AT45DB161B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 4223 BIT PAGE n PAGE n DATA OUT MSB D 5 2224I–DFLSH–10/04 ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued) Buffer Read (Opcode: 54H or 56H) CS SCK COMMAND OPCODE Status Register Read (Opcode: 57H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO 2224I–DFLSH–10/ HIGH-IMPEDANCE AT45DB161B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB 19 ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity High Continuous Array Read (Opcode: 68H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE AT45DB161B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 4223 BIT PAGE n PAGE n DATA OUT MSB D 4 2224I–DFLSH–10/04 ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued) Buffer Read (Opcode: 54H or 56H) CS SCK COMMAND OPCODE Status Register Read (Opcode: 57H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO 2224I–DFLSH–10/ HIGH-IMPEDANCE AT45DB161B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB 21 ...
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... Detailed Bit-level Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB161B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 4223 BIT PAGE n PAGE n DATA OUT MSB D 4 2224I–DFLSH–10/04 ...
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... Detailed Bit-level Read Timing – SPI Mode 0 (Continued) Buffer Read (Opcode: D4H or D6H) CS SCK COMMAND OPCODE Status Register Read (Opcode: D7H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO 2224I–DFLSH–10/ HIGH-IMPEDANCE AT45DB161B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB 23 ...
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... Detailed Bit-level Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB161B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 4223 BIT PAGE n PAGE n DATA OUT MSB D 4 2224I–DFLSH–10/04 ...
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... Detailed Bit-level Read Timing – SPI Mode 3 (Continued) Buffer Read (Opcode: D4H or D6H) CS SCK COMMAND OPCODE Status Register Read (Opcode: D7H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO 2224I–DFLSH–10/ HIGH-IMPEDANCE AT45DB161B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB 25 ...
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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB161B 26 START provide address ...
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... END PA8 PA7 PA6 • • • • • • • • • AT45DB161B If planning to modify multiple bytes currently stored within a page of the Flash array (84H, 87H) (83H, 86H) PA5 PA4 PA3 • • • • • • • • • ...
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... Wide, Plastic Gull Wing Small Outline Package (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) AT45DB161B 28 Ordering Code AT45DB161B-CC-2.5 AT45DB161B-CNC-2.5 AT45DB161B-RC-2.5 AT45DB161B-TC-2.5 AT45DB161B-CC AT45DB161B-CNC AT45DB161B-RC AT45DB161B-TC AT45DB161B-CI AT45DB161B-CNI AT45DB161B-RI AT45DB161B-TI Ordering Code AT45DB161B-CNU AT45DB161B-RU AT45DB161B-TU Package Type Package Operation Range 24C1 Commercial 8CN3 ( 2.5V to 3.6V 28R 28T ...
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... BOTTOM VIEW TITLE 24C1, 24-ball ( Array 1.4 mm Body, 1.0 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) AT45DB161B SIDE VIEW 0.30 (0.012)MIN 1.40 (0.055) MAX 2.00 (0.079) REF 4.0 (0.157) 0.46 (0.018) DIA BALL TYP DRAWING NO. 04/11/01 REV. 24C1 A 29 ...
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... All dimensions and tolerance conform to ASME Y 14.5M, 1994. 2. The surface finish of the package shall be EDM Charmille #24-27. 3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2 4. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB161B 30 D Top View Side View Pin1 Pad Corner L1 ...
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... Mold Flash or protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 2224I–DFLSH–10/ TITLE 28R, 28-lead, 0.330" Body Width, Plastic Gull Wing Small Outline (SOIC) AT45DB161B COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A 2.39 – 2.79 A1 0.050 – 0.356 D 18 ...
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... E Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB161B 32 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) 0º ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...