AT45DB642-TI Atmel, AT45DB642-TI Datasheet
AT45DB642-TI
Specifications of AT45DB642-TI
Available stocks
Related parts for AT45DB642-TI
AT45DB642-TI Summary of contents
Page 1
... The AT45DB642 is a 2.7-volt only, dual-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The dual-interface of the AT45DB642 allows a dedicated serial interface to be connected to a DSP and a dedicated parallel interface to be connected to a microcontroller or vice versa. ...
Page 2
... However, the use of either interface is purely optional. Its 69,206,016 bits of memory are orga- nized as 8192 pages of 1056 bytes each. In addition to the main memory, the AT45DB642 also contains two SRAM data buffers of 1056 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed, as well as reading or writing a con- tinuous data stream ...
Page 3
... BLOCK 0 SECTOR 0 BLOCK 1 BLOCK 2 BLOCK 30 BLOCK 31 BLOCK 32 BLOCK 33 BLOCK 62 BLOCK 63 BLOCK 64 BLOCK 65 BLOCK 1022 BLOCK 1023 Block = 8448 bytes (8K + 256) AT45DB642 PAGE ARCHITECTURE 8 Pages PAGE 0 PAGE 1 PAGE 6 PAGE 7 PAGE 8 PAGE 9 PAGE 14 PAGE 15 PAGE 16 PAGE 17 PAGE 18 PAGE 8189 PAGE 8190 PAGE 8191 ...
Page 4
... The don't care bytes that follow the three address bytes are needed to initialize the read operation. Following the don't care bytes, additional clock pulses on the SCK/CLK pin will result in data being output on either the SO pin or the I/O7-I/O0 pins. AT45DB642 4 specification. The Continuous Array Read bypasses both data CAR 1638F– ...
Page 5
... When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pins (SO or I/O7 - I/O0). 1638F–DFLSH–09/02 AT45DB642 specification. The Burst Array Read with Syn- BARSD 5 ...
Page 6
... The device density is indicated using bits and 2 of the status register. For the AT45DB642, the four bits are logical “1”s. The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices, allowing a total of sixteen different density configurations ...
Page 7
... RDY/BUSY pin will indicate that the part is busy. 1638F–DFLSH–09/02 . During this time, the status register and the RDY/BUSY pin will indicate that the EP . During this time, the status register and the RDY/BUSY pin will indicate P AT45DB642 . During this PE . During this time, the status register and BE 7 ...
Page 8
... The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (t register can be read or the RDY/BUSY can be monitored to determine whether the transfer has been completed. AT45DB642 8 PA8 PA7 ...
Page 9
... If a Group A mode is in progress (not fully completed), then another mode in Group A should not be started. However, during this time in which a Group A mode is in progress, modes in Group B can be started. 1638F–DFLSH–09/02 . During this time, the status register and the RDY/BUSY pin will indi- EP AT45DB642 ), the XFR 9 ...
Page 10
... The WP pin is internally pulled high; therefore, in low pin count applications, con- nection of the WP pin is not necessary if this pin and feature will not be utilized. However recommended that the WP pin be driven high externally whenever possible. AT45DB642 10 (SER/PAR Setup time) requirements should be followed. ...
Page 11
... DataFlash occur during the programming and erase operation. The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. 1638F–DFLSH–09/02 AT45DB642 11 ...
Page 12
... Auto Page Rewrite Through Buffer 2 Note: In Tables 2 and 3, an SCK/CLK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3). AT45DB642 12 SCK/CLK Mode Inactive Clock Polarity Low or High ...
Page 13
... P D4H D6H D7H E8H E9H Note Page Address Bit B = Byte/Buffer Address Bit x = Don’t Care * 4 Bytes for Serial Interface 60 Bytes for Parallel Interface 1638F–DFLSH–09/02 Address Byte Address Byte N/A N N/A N AT45DB642 Address Byte N N Additional Don’t Care Bytes ...
Page 14
... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB642 0°C to 70°C -40°C to 85°C 2.7V to 3.6V Min Typ ...
Page 15
... Page Erase and Programming Time EP t Page Programming Time P t Page Erase Time PE t Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC 1638F–DFLSH–09/02 AT45DB642 Min Max Units 100 ns 100 ns Min Max Units 20 MHz 15 MHz 20 MHz 22 ...
Page 16
... Page Programming Time P t Page Erase Time PE t Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC Test Waveforms and Measurement Levels Output Test Load AT45DB642 16 2. 2.0 DRIVING MEASUREMENT 0.8 LEVELS LEVEL 0.45V tR, tF < (10% to 90%) DEVICE UNDER TEST ...
Page 17
... SI or I/O7 - I/O0 1638F–DFLSH–09/02 CS tCSS tWH SCK/CLK HIGH IMPEDANCE (OUTPUT) tSU VALID IN (INPUT) CS tCSS tWL tWH SCK/CLK tV HIGH Z VALID OUT (OUTPUT) tSU VALID IN (INPUT) AT45DB642 tCS tWL tCSH tV tHO tDIS HIGH IMPEDANCE VALID OUT tH tCS tCSH tHO HIGH IMPEDANCE tH tDIS 17 ...
Page 18
... SI or I/O7 - I/O0 (INPUT) Note: The CS signal should be in the high state before the RESET signal is deasserted. Serial/Parallel Interface Timing CS SER/PAR Command Sequence for Read/Write Operations (Except Status Register Read I/O7 - I/O0 (INPUT) MSB AT45DB642 18 HIGH IMPEDANCE t SPH CMD 8 bits 8 bits Page Address ...
Page 19
... PA12-5 PA4-0, BFA10-8 BFA7-0 X X···X, BFA10-8 BFA7-0 Starts self-timed erase/program operation CS CMD PA12-5 AT45DB642 BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 (1056 BYTES) BUFFER 2 WRITE I/O7 - I/O0 · Completes writing into selected buffer · Starts self-timed erase/program operation ...
Page 20
... Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer I/ I/O7 - I/O0 Buffer Read I/O7 - I/O0 (INPUT I/O7 - I/O0 (OUTPUT) Each transition represents 8 bits AT45DB642 20 FLASH MEMORY ARRAY BUFFER 2 (1056 BYTES) MAIN MEMORY PAGE READ I/O INTERFACE I/O7 - I/O0 SO PA12-5 PA4-0, BA10-8 ...
Page 21
... HIGH IMPEDANCE SO Burst Array Read with Synchronous Delay (Opcode: 69H) CS SCK 1 2 tSU HIGH IMPEDANCE SO 1638F–DFLSH–09/ DATA OUT DATA OUT AT45DB642 LSB MSB BIT 8447 BIT PAGE n PAGE n CLOCKS LSB D 0 Don't Care BIT 8447 OF PAGE n PAGE n+1 MSB BIT ...
Page 22
... Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued) Main Memory Page Read (Opcode: 52H) CS SCK 1 2 tSU COMMAND OPCODE Buffer Read (Opcode: 54H or 56H) CS SCK 1 2 tSU COMMAND OPCODE Status Register Read (Opcode: 57H) CS SCK tSU COMMAND OPCODE HIGH IMPEDANCE SO AT45DB642 HIGH IMPEDANCE HIGH IMPEDANCE ...
Page 23
... HIGH IMPEDANCE SO Burst Array Read with Synchronous Delay (Opcode: 69H) CS SCK 1 2 tSU HIGH IMPEDANCE SO 1638F–DFLSH–09/ DATA OUT DATA OUT AT45DB642 LSB MSB BIT 8447 BIT PAGE n PAGE n CLOCKS LSB Don't Care D 0 BIT 8447 OF PAGE n PAGE n+1 MSB BIT ...
Page 24
... Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued) Main Memory Page Read (Opcode: 52H) CS SCK tSU COMMAND OPCODE Buffer Read (Opcode: 54H or 56H) CS SCK tSU COMMAND OPCODE Status Register Read (Opcode: 57H) CS SCK tSU COMMAND OPCODE HIGH IMPEDANCE SO AT45DB642 HIGH IMPEDANCE HIGH IMPEDANCE MSB ...
Page 25
... HIGH IMPEDANCE SO Burst Array Read with Synchronous Delay (Opcode: E9H) CS SCK 1 2 tSU HIGH IMPEDANCE SO 1638F–DFLSH–09/ DATA OUT DATA OUT AT45DB642 LSB MSB BIT 8447 BIT PAGE n PAGE n CLOCKS LSB MSB Don't Care BIT 8447 BIT PAGE n PAGE n ...
Page 26
... Detailed Bit-level Read Timing – SPI Mode 0 (Continued) Main Memory Page Read (Opcode: D2H) CS SCK 1 2 tSU COMMAND OPCODE Buffer Read (Opcode: D4H or D6H) CS SCK 1 2 tSU COMMAND OPCODE Status Register Read (Opcode: D7H) CS SCK tSU COMMAND OPCODE HIGH IMPEDANCE SO AT45DB642 HIGH IMPEDANCE HIGH IMPEDANCE ...
Page 27
... HIGH IMPEDANCE SO Burst Array Read with Synchronous Delay (Opcode: E9H) CS SCK 1 2 tSU HIGH IMPEDANCE SO 1638F–DFLSH–09/ DATA OUT DATA OUT AT45DB642 LSB MSB BIT 8447 BIT PAGE n PAGE n CLOCKS LSB MSB D 0 Don't Care D 7 BIT 8447 BIT PAGE n PAGE n ...
Page 28
... Detailed Bit-level Read Timing – SPI Mode 3 (Continued) Main Memory Page Read (Opcode: D2H) CS SCK tSU COMMAND OPCODE Buffer Read (Opcode: D4H or D6H) CS SCK tSU COMMAND OPCODE Status Register Read (Opcode: D7H) CS SCK tSU COMMAND OPCODE HIGH IMPEDANCE SO AT45DB642 HIGH IMPEDANCE HIGH IMPEDANCE MSB ...
Page 29
... HIGH IMPEDANCE I/O7-I/O0 (OUTPUT) 1638F–DFLSH–09/ DATA OUT DATA DATA DATA DATA OUT DATA DATA DATA AT45DB642 DATA DATA DATA DATA DATA DATA BYTE 1055 BYTE PAGE n PAGE n CLOCKS Don't Care DATA DATA DATA BYTE 1055 BYTE PAGE n PAGE n+1 29 ...
Page 30
... CLK 1 2 tSU COMMAND OPCODE I/O7-I/O0 ADDR CMD (INPUT) I/O7-I/O0 (OUTPUT) Buffer Read (Opcode: D4H or D6H) CS CLK I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) Status Register Read (Opcode: D7H) I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) AT45DB642 ADDR ADDR HIGH IMPEDANCE tSU COMMAND OPCODE ADDR ADDR ADDR ...
Page 31
... HIGH IMPEDANCE I/O7-I/O0 (OUTPUT) 1638F–DFLSH–09/ DATA OUT DATA DATA DATA DATA OUT DATA DATA DATA BYTE 1055 AT45DB642 DATA DATA DATA DATA DATA DATA BYTE 1055 BYTE PAGE n PAGE n CLOCKS DON'T CARE DATA DATA DATA BYTE PAGE n PAGE n+1 31 ...
Page 32
... COMMAND OPCODE I/07-I/O0 ADDR ADDR ADDR CMD (INPUT) I/07-I/O0 (OUTPUT) Buffer Read (Opcode: D4H or D6H) CS CLK I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) Status Register Read (Opcode: D7H) CS CLK I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) AT45DB642 HIGH IMPEDANCE tSU CMD ADDR ADDR ADDR X tV HIGH IMPEDANCE ...
Page 33
... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 1638F–DFLSH–09/02 START provide address and data MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) MEMORY PAGE PROGRAM END AT45DB642 BUFFER WRITE (84H, 87H) BUFFER TO MAIN (83H, 86H) 33 ...
Page 34
... AT45DB642 34 START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) BUFFER WRITE (84H, 87H) (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) (2) AUTO PAGE REWRITE (58H, 59H) INCREMENT PAGE (2) ADDRESS POINTER ...
Page 35
... CC SCK (MHz) Active Standby (1) ( 0.01 (1) ( 0.01 Note: 1. Serial Interface 40T 40-lead, Plastic Thin Small Outline Package (TSOP) 1638F–DFLSH–09/02 Ordering Code AT45DB642-TC AT45DB642-TI Package Type AT45DB642 Package Operation Range 40T Commercial (0°C to 70°C) 40T Industrial (-40°C to 85°C) 35 ...
Page 36
... This package conforms to JEDEC reference MO-142, Variation CD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. TITLE 2325 Orchard Parkway San Jose, CA 95131 R AT45DB642 36 PIN 1 0º ~ 8º SEATING PLANE ...
Page 37
... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...