AT45DB642-TI Atmel, AT45DB642-TI Datasheet - Page 3

• Manufacturer Part Number: AT45DB642-TI
• Description: IC FLASH 64MBIT 20MHZ 40TSOP
• Manufacturer: Atmel

Specifications of AT45DB642-TI

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 20MHz Serial/5MHz Parallel
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Memory Architecture Diagram
Device
Operation
Read Commands
1638F–DFLSH–09/02
SECTOR ARCHITECTURE
261,888 bytes (248K + 7936)
270,336 bytes (256K + 8K)
270,336 bytes (256K + 8K)
270,336 bytes (256K + 8K)
270,336 bytes (256K + 8K)
SECTOR 31 = 256 Pages
SECTOR 32 = 256 Pages
SECTOR 2 = 256 Pages
SECTOR 3 = 256 Pages
SECTOR 1 = 248 Pages
8448 bytes (8K + 256)
SECTOR 0 = 8 Pages
The device operation is controlled by instructions from the host processor. The list of instruc-
tions and their associated opcodes are contained in Tables 1 through 4. A valid instruction
starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired
buffer or main memory address location. While the CS pin is low, toggling the SCK/CLK pin
controls the loading of the opcode and the desired buffer or main memory address location
through either the SI (serial input) pin or the parallel input pins (I/O7 - I/O0). All instructions,
addresses, and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA10 - BFA0 to
denote the 11 address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology PA12 - PA0 and BA10 - BA0, where PA12 -
denotes the 11 address bits required to designate a byte address within the page.
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two SRAM data buffers. The DataFlash supports two categories of read modes in
relation to the SCK/CLK signal. The differences between the modes are in respect to the inac-
tive state of the SCK/CLK signal as well as which clock cycle data will begin to be output. The
two categories, which are comprised of four modes total, are defined as Inactive Clock Polarity
Low or Inactive Clock Polarity High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer
to Table 1 for a complete list) is used to select which category will be used for reading. Please
refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock
cycle sequences for each mode.
PA0 denotes the 13 address bits required to designate a page address and BA10 - BA0
SECTOR 0
BLOCK ARCHITECTURE
Block = 8448 bytes
BLOCK 1022
BLOCK 1023
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 0
BLOCK 1
BLOCK 2
(8K + 256)
8 Pages
PAGE ARCHITECTURE
Page = 1056 bytes
AT45DB642
PAGE 8189
PAGE 8190
PAGE 8191
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
(1K + 32)
3