AT25256AW-10SI-1.8 Atmel, AT25256AW-10SI-1.8 Datasheet - Page 7

• Manufacturer Part Number: AT25256AW-10SI-1.8
• Description: IC EEPROM 256KBIT 20MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25256AW-10SI-1.8

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 5MHz, 10MHz, 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT25256AW-10SI1.8

2. Serial Interface Description
3368J–SEEPR–06/07
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128A/256A always
operates as a slave.
TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for data
transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25128A/256A, and the serial output pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25128A/256A is selected when the CS pin is low. When the device is not
selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a
high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128A/256A.
When the device is selected and a serial sequence is underway, HOLD can be used to pause
the serial communication with the master device without resetting the serial sequence. To
pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communi-
cation, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held
high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status reg-
ister are inhibited. WP going low while CS is still low will interrupt a write to the status register. If
the internal write cycle has already been initiated, WP going low will have no effect on any write
operation to the status register. The WP pin function is blocked when the WPEN bit in the status
register is “0”. This will allow the user to install the AT25128A/256A in a system with the WP pin
tied to ground and still be able to write to the status register. All WP pin functions are enabled
when the WPEN bit is set to “1”.
AT25128A_256A
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