AT49F040A-70TU SL383 Atmel, AT49F040A-70TU SL383 Datasheet
AT49F040A-70TU SL383
Specifications of AT49F040A-70TU SL383
Related parts for AT49F040A-70TU SL383
AT49F040A-70TU SL383 Summary of contents
Page 1
... Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus conten- tion. Reprogramming the AT49F040A is performed by erasing a block of data and then programming on a byte-by-byte basis. The byte programming time is a fast 20 µ ...
Page 2
... Pin Configurations Pin Name A0 - A18 I/O0 - I/O7 2.1 32-lead PLCC Top View 2.2 32-lead TSOP (Type 1) Top View ( mm) AT49F040A 2 Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs I/ A11 A13 4 A14 5 A17 VCC 8 A18 9 A16 10 A15 11 A12 A14 A13 A8 A9 ...
Page 3
... Device Operation 4.1 Read The AT49F040A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever high. This dual-line con- trol gives designers flexibility in preventing bus contention. 3359D– ...
Page 4
... The program cycle has addresses latched on the falling edge CE, whichever occurs last, and the data latched on the rising edge CE, whichever occurs first. Programming is completed after the specified t indicate the end of a program cycle. AT49F040A 4 6. The command sequences are written by applying a low “Command Definition Table” on page cycle time ...
Page 5
... DATA Polling The AT49F040A features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin ...
Page 6
... Temperature Under Bias................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0. Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V AT49F040A 6 1st Bus 2nd Bus 3rd Bus Cycle Cycle Cycle Data ...
Page 7
... A18 = A18 = Condition MHz OUT -400 µ -100 µ 4. AT49F040A AT49F040A-55 AT49F040A-70 -40°C - 85°C -40°C - 85°C 5V ± 10% 5V ± Manufacturer Code ( A18 =V Manufacturer Code A18 = Min Max 0.8 2.0 0.45 2.4 4.2 I/O D OUT D IN High Z High Z High Z (4) ...
Page 8
... This parameter is characterized and is not 100% tested. AT49F040A 8 AT49F040A-55 Min (1)(2)(3)(4) ADDRESS ADDRESS VALID ACC HIGH Z OUTPUT OUTPUT - t after the address transition without impact on t ACC after the falling edge of CE without impact AT49F040A-70 Max Min Max VALID . ACC after an address change CE ACC OE Units ns ns ...
Page 9
... Input Test Waveform and Measurement Level < 15. Output Load Test 16. Pin Capacitance ( MHz 25°C Symbol Typ OUT Note: 1. This parameter is characterized and is not 100% tested. 3359D–FLASH–3/ 5.0V 1.8K OUTPUT PIN 30 pF 1.3K Max Units AT49F040A Conditions OUT 9 ...
Page 10
... CS t Chip Select Hold Time CH t Write Pulse Width ( Data Set-up Time Data, OE Hold Time DH OEH t Write Pulse Width High WPH 18. AC Byte Load Waveforms 18.1 WE Controlled OE ADDRESS CE WE DATA IN 18.2 CE Controlled OE ADDRESS WE CE DATA IN AT49F040A OES OEH OES t OEH ...
Page 11
... For chip erase, the address should be 555. For sector erase, the address depends on what sector erased. (See note 4 under “Command Definition Table” on page 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. 3359D–FLASH–3/05 Min Typ 6.) AT49F040A Max Units 40 µ seconds 11 ...
Page 12
... Read Characteristics” OE 25. Toggle Bit Waveforms I/O6 Notes: 1. Toggling either both OE and CE will operate toggle bit. The t input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. AT49F040A 12 (1) Min OEH t OE ...
Page 13
... LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION (4) MODE Notes: 1. Data Format: I/O7 - I/O0 (Hex); 2. Boot block lockout feature enabled AT49F040A (1) LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 80 TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 ...
Page 14
... Ordering Code Package AT49F040A-55JI 32J AT49F040A-55TI 32T AT49F040A-70JI 32J AT49F040A-70TI 32T Ordering Code Package AT49F040A-55JU 32J AT49F040A-55TU 32T AT49F040A-70JU 32J AT49F040A-70TU 32T Package Type Operation Range Industrial (-40° to 85°C) Industrial (-40° to 85°C) Operation Range Industrial (-40° to 85°C) Industrial (-40° ...
Page 15
... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3359D–FLASH–3/05 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) AT49F040A 0.318(0.0125) 0.191(0.0075 COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 3.175 – ...
Page 16
... E Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49F040A 16 PIN SEATING PLANE A1 TITLE ...
Page 17
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...