AT49LH004-33JC Atmel, AT49LH004-33JC Datasheet - Page 9

• Manufacturer Part Number: AT49LH004-33JC
• Description: IC FLASH 4MBIT 33MHZ 32PLCC
• Manufacturer: Atmel

Specifications of AT49LH004-33JC

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.3.5
7.3.6
7.3.7
7.4
3383D–FLASH–6/05
FWH Read Cycle
Additional Fields for FWH Memory Cycles
TAR (Turn-around) Field
SYNC (Synchronize) Field
Additional fields are required to complete a FWH read or write cycle. The placement of these
fields, in addition to the data field, depends on whether the cycle is a FWH read or write. The
FWH Read Cycle and FWH Write Cycle sections detail the order of the various fields.
This 2-clock field is driven by the master when it is turning control over to the FWH memory
device, and it is driven by the FWH device when it is turning control back over to the master.
On the first clock of the TAR field, the master or FWH drives the FWH/LAD[3:0] lines to 1111b.
On the second clock, the master or FWH device puts the FWH/LAD[3:0] lines into a high-
impedance state.
This field is used to add wait-states for an access. It can be several clocks in length. On target
cycles, this field is driven by the FWH memory device. If the FWH device needs to assert wait-
states, it does so by driving a “wait” SYNC value of 0101b on the FWH/LAD[3:0] pins until it is
ready. When ready, the device will drive a “ready” SYNC value of 0000b on the FWH/LAD[3:0]
lines. Valid values for the SYNC field are shown in
Table 7-2.
FWH read cycles are used to read data from the memory array, the Sector Locking Registers,
the GPI register, the Status Register, and to read the product ID information. Upon initial
device power-up or after exiting from a reset condition, the device will automatically default to
the read array mode.
Valid FWH read cycles begin with a START field of 1101b being sent to the device. Following
the IDSEL, MADDR, and MSIZE fields, a 2-clock TAR field must be sent to the device to indi-
cate that the master is turning control of the LPC bus over to the FWH memory device. After
the second clock of the TAR phase, the FWH device assumes control of the bus and begins
driving SYNC fields to add wait-states. When the device is ready to output data, it will first
send a “ready” SYNC and then output one byte of data during the next two clock cycles. The
data is sent one nibble at a time with the low nibble being output first followed by the high nib-
ble. After the data has been output, the FWH device will send a 2-clock TAR field to the master
to indicate that it is turning control of the LPC bus back over to the master.
Table 7-2
memory array.
SYNC Value
0000b
0101b
shows a FWH read cycle that requires three SYNC clocks to access data from the
Valid SYNC Values
SYNC Type
RSYNC (Ready SYNC) – Synchronization has been achieved with no error.
WSYNC (Wait SYNC) – Device is indicating wait-states (also referred to as short-
sync).
Table
7-2.
AT49LH004
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