AT49LH004-33JX Atmel, AT49LH004-33JX Datasheet
AT49LH004-33JX
Specifications of AT49LH004-33JX
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AT49LH004-33JX Summary of contents
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... Green (Pb/Halide-free) Packaging Option 1. Description The AT49LH004 is a Flash memory device designed for use in PC and notebook BIOS applications. The device complies with version 1.1 of Intel’s LPC Interface Spec- ification, providing support for both FWH and LPC memory read and write cycles. The device can also automatically detect the memory cycle type to allow the AT49LH004 to be used as a FWH with Intel chipsets LPC Flash with non-Intel chipsets ...
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... The memory array of the AT49LH004 can be sectored in two ways simply by using two differ- ent erase commands. Using one erase command allows the device to contain a total of 11 sectors comprised of a 32-Kbyte boot sector, two 8-Kbyte sectors, a 16-Kbyte sector, and seven 64-Kbyte sectors. The 32-Kbyte boot sector is located at the top (uppermost) of the device’ ...
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... Sub-sector 7 Sub-sector 6 Main Sector 5 Main Sector 4 Main Sector 3 Main Sector 2 Main Sector 1 Main Sector 0 Main Sector AT49LH004 I/O BUFFERS CONTROL LOGIC AND LATCHES Y-DECODER Y-GATING FLASH MEMORY X-DECODER ARRAY Size (Bytes) Address Range 32K 078000H - 07FFFFH 8K 076000H - 077FFFH 8K 074000H - 075FFFH 16K ...
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... If the TBL pin is held high, then hardware write protection for the top boot sector will be disabled. However, register-based sector protection will still apply. The state of the TBL pin does not affect the state of the Sector Locking Registers. This pin is used as the A4 pin in the A/A Mux interface. AT49LH004 4 Interface FWH/LPC ...
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... The I/O[7:0] pins will be in high-impedance state when the OE pin is deasserted (high). WRITE ENABLE: The WE pin is used in the A/A Mux interface to control write WE operations to the device. 3383D–FLASH–6/05 See “Sector Protection” on page 17. for more and V IH AT49LH004 Interface FWH/LPC A/A Mux Type X Input X Input X ...
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... These pins are used as the RDY/BSY and I/O[7:4] pins in the A/A Mux interface. 6. Interface Selection The AT49LH004 can operate in two distinct interface modes: The FWH/LPC interface and the A/A Mux interface. Selection of the interface is determined by the state of the IC pin. When the IC pin is held low, the device will operate using the FWH/LPC interface ...
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... Since the AT49LH004 can be used as either a FWH Flash or an LPC Flash, the device is capable of automatically detecting which type of memory cycle is being performed. For a FWH/LPC cycle, the host will drive the FWH4/LFRAME pin low for one or more clock cycles to initiate the operation. After driving the FWH4/LFRAME pin low, the host will send a START value to indicate the type of FWH/LPC cycle that performed ...
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... MB per FWH memory device, for a total addressable space if 16 FWH memory devices (256 MB each) were used in a system. The AT49LH004 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits A27 - A23 and A21 - A19. Address bit A22 is used to determine whether reads or writes to the device will be directed to the memory array (A22 = the register space (A22 = 0) ...
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... Valid SYNC Values SYNC Type RSYNC (Ready SYNC) – Synchronization has been achieved with no error. WSYNC (Wait SYNC) – Device is indicating wait-states (also referred to as short- sync). shows a FWH read cycle that requires three SYNC clocks to access data from the AT49LH004 Table 7-2. 9 ...
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... TAR1 1111b (float WSYNC 0101b (wait) 15 RSYNC 0000b (ready) 16 DATA 17 DATA 18 TAR0 19 TAR1 1111b (float) Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LH004 A15-A12 A11-A8 A7-A4 A3-A0 0000b MADDR MSIZE (1) FWH/LAD[3:0] Direction Comments FWH4/LFRAME must be active (low) for the device to respond ...
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... OUT data byte has been received. OUT then float The FWH memory device drives the bus to 1111b to indicate a turn-around cycle. The FWH memory device floats its outputs, and the master regains control of the Float then IN bus during this clock cycle. AT49LH004 ...
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... Bit[1] is used to determine the direction of the transfer used to indicate a read, and 1 is used to indicate a write. Bit[0] is ignored and reserved for future use. valid CYCTYPE + DIR fields that the device will respond to. Table 7-5. FWH/LAD[3:0] 010xb 011xb AT49LH004 12 LPC Memory Cycle Initiation and Addressing CLK CYCTYPE START MADDR MADDR MADDR ...
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... This is an 8-clock field that is used to provide a 32-bit (A31 - A0) memory address. The 32 address bits allow for the provisioning to access memory space. The AT49LH004 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits A31 - A24. Address bit A23 is used to determine whether reads or writes to the device will be directed to the memory array (A23 = the register space (A23 = 0) ...
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... RSYNC 0000b (ready) 16 DATA 17 DATA 18 TAR0 19 TAR1 1111b (float) Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LH004 14 shows a LPC read cycle that requires three SYNC clocks to access data from the A23-A20 A19-A16 A15-A12 A11-A8 A7-A4 A3-A0 ...
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... SYNC indicating that the data byte has been received. The LPC memory device drives the bus to 1111b to indicate a 1111b OUT then float turn-around cycle. The LPC memory device floats its outputs, and the master Float then IN regains control of the bus during this clock cycle. AT49LH004 A3-A0 ...
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... As long as the states of FWH/LAD[3:0] and FWH4/LFRAME are known, the response of the device to signals received during the LPC cycle should be predictable. The device will make no attempt to check the validity of incoming Flash operation commands. AT49LH004 16 3383D–FLASH–6/05 ...
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... In addition, when operating in LPC mode, the TBL pin has the flexibility to provide erase 3383D–FLASH–6/05 Table 7-4 and Table 7-8) and no internal Flash operation will be using the FWH/LPC interface and t PHFV AT49LH004 time (FWH/LPC and A/A Mux PLPH using the A/A Mux inter- PHAV 17 ...
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... AT49LH004 18 Hardware Write Protection FWH Mode For All For the Following Program and Commands: Erase Sector Erase (21H) Commands Byte Program (40H or 10H) TBL TBL TBL ...
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... In FWH mode, these registers are treated as one; therefore, only one Sector Locking Regis- ter is available for all sub-sectors (sectors 10 and 7) and the sub-sectors cannot be individually protected. The default value for this register is 01H. AT49LH004 Table 11-2) in the 4 GB sys- Register Memory Address ...
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... The Lock-Down bit is only cleared upon a device reset with RST or INIT or after a power-up. The current lock down status of a particular sector can be determined by reading the corresponding Lock-Down bit. AT49LH004 20 3383D–FLASH–6/05 ...
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... The Read-Lock and Write-Lock bits cannot be changed. Once the sector is locked down, it will remain locked down until the device is reset (using the RST or INIT signals) or power-cycled. Sector is not write-locked. Normal program and erase operations to the sector can occur. Sector is write-locked. Program and erase operations to the sector are prevented. This is the default state. AT49LH004 21 ...
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... The boot device must have ID[3:0] equal to 0000b, and all subsequent devices should use sequential up-count strapping. AT49LH004 22 GPI Register Memory Address Register Memory Address ...
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... FWH4/LFRAME pin is high and no internal operation is in progress. The FWH/LAD[3:0] pins will also be placed in a high-impedance state. Table 13-1. 0 (Boot Device) 3383D–FLASH–6/05 FWH Multiple Device Selection Device ID3 AT49LH004 ID Strapping Pins ID2 ID1 ID0 ...
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... The A/A Mux interface mode is selected by driving the IC control pin high. The IC pin is inter- nally pulled down in the device modest amount of leakage current should be expected to be drawn (see DC Specifications) when the pin is driven high. AT49LH004 24 LPC Multiple Device Selection ID Strapping Pins ...
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... and V refer to the DC characteristics associated with the Flash memory output buffers min = 0.5V, V max = 0.8V Refer to Table 16-2 for Product ID addresses and data. ), the device outputs are disabled. Output pins I/O[7:0] are IH AT49LH004 OE WE Address ...
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... In addition, the Sector Erase command can be used to erase the main sectors as well to allow a single erase command to be used to erase any sector in the memory array. Both sector erase commands require two command cycles to initiate the internally self- timed erase operation. AT49LH004 26 1st Command Cycle Type ...
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... Clear Status Register Error flags (SR[5,4,1]) in the Status Register can only be set to “1”s by the WSM and can only be reset by the Clear Status Register command. Therefore error is detected, the Status Register must be cleared before beginning another operation to avoid ambiguity. 3383D–FLASH–6/05 AT49LH004 27 ...
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... Product ID Read mode, any valid command can be written to the device. Table 16-2. Product ID Address and Data Code Manufacturer ID Device ID AT49LH004 28 Device is BUSY. A program or erase cycle is in progress. SR[6-1] values are invalid when SR[ Device is READY. The device is ready for any operation. ...
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... PCI output V and V spec AT49LH004 Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional oper- ation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied ...
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... I High Clamp Current CH slewr Output Rise Slew Rate slewf Output Fall Slew Rate Notes: 1. PCI specification output load is used (98.0 OUT (256 OUT CC AT49LH004 30 Conditions 0 < V < -500 µA OUT I = 1.5 mA OUT Condition ≤ 0 < V OUT CC 0.3 V < V < 0 OUT CC 0.7 V < ...
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... CLK to Data Out (2) CLK to Active (Float to Active Delay) CLK to Inactive (Active to Float Delay) (3) Input Set-up Time (3) Input Hold Time Reset Active Time after Power Stable Reset Active Time after CLK Stable (2) Reset Active to Output Float Delay AT49LH004 Min Max 30 • LOW ...
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... RST or INIT Pulse Low Time (If RST or INIT is tied to V (1) t PLPH specification is not applicable) t RST or INIT High to FWH4/FRAME Low PHFV Note reset latency of 20 µs will occur if a reset procedure is performed during a programming or erase operation. AT49LH004 32 CLK V TEST t VAL FWH/LAD[3:0] FWH/LDA[3:0] t ...
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... IL 4. Refer to PCI spec. 3383D–FLASH–6/ PLPH PHFV (1) Typ 30 150 = +25°C and nominal voltages. A Conditions max GND OUT min -2 min -100 µ min AT49LH004 Max Unit 50 µs 500 ms Min Max 0 0 -0.5 0.8 +10 0.85 V min 0 Unit V V µ ...
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... If RST is asserted when the WSM is not busy (RDY/BSY = 1), the reset will complete within 100 ns reset recovery time, t PHAV 32. AC Waveforms for Reset Operations V IH RDY/BSY RST ADDRESS V IL AT49LH004 34 , this specification is not CC (1)(2) ( required from the latter of RDY/BSY or RST going high until addresses are valid. t PLRH t t PLPH PHAV Min Max 100 ...
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... R/C without impact on t CHQV GLQV t AVAV Row Address Column Address Stable Stable t t CLAX AVCH t CHAX t CHQV High-Z t GLQX AT49LH004 Min Max 250 150 CHQV Next Address Stable t GLQV t GHQZ t QXGH Data Valid ...
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... V IH RDY/BSY RST V IL NOTES power-up and standby Write sector erase or program setup C = Write sector erase confirm or valid address and data D = Automated erase or program delay E = Read status register data F = Ready to write another command AT49LH004 36 ( AVCH t t CLAX CHAX t CHWH t t PHWL ...
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... Plastic J-leaded Chip Carrier Package (PLCC) 40T 40-lead, Thin Small Outline Package (TSOP) 3383D–FLASH–6/05 Ordering Code AT49LH004-33JC AT49LH004-33TC Ordering Code AT49LH004-33JX AT49LH004-33TX Package Type AT49LH004 Package Operation Range 32J Extended Commercial 40T (0° to 85°C) Package ...
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... Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010 (0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004 (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49LH004 38 1.14(0.045 PIN NO. 1 IDENTIFIER ...
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... E is 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3383D–FLASH–6/05 PIN SEATING PLANE A1 TITLE 40T, 40-lead ( Package) Plastic Thin Small Outline Package, Type I (TSOP) AT49LH004 GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – – ...
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