AT49LH004-33JX Atmel, AT49LH004-33JX Datasheet - Page 17

• Manufacturer Part Number: AT49LH004-33JX
• Description: IC FLASH 4MBIT 33MHZ 32PLCC
• Manufacturer: Atmel

Specifications of AT49LH004-33JX

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9. Bus Abort
10. Device Reset
11. Sector Protection
11.1
3383D–FLASH–6/05
Hardware Write Protection
The Bus Abort operation can be used to immediately abort the current bus operation. A Bus
Abort occurs when FWH4/LFRAME is driven low for one or more clock cycles after the start of
a bus cycle. The memory will place the FWH/LAD[3:0] pins in a high-impedance state, and the
internal state machine will reset. During a write cycle, there is the possibility that an internal
Flash write or erase operation may be in progress (or has just been initiated). If the
FWH4/LFRAME pin is asserted during this time frame, the internal operation will not abort.
However, the internal state machine will not initiate a Flash write or erase operation until it has
received the last nibble from the host. This means that FWH4/LFRAME can be asserted as
late as clock cycle 12 (see
attempted.
When the FWH4/LFRAME pin has been driven low to abort a cycle, the host may issue a
START field of 1111b (stop/abort) to return the interface to the ready mode.
Asserting RST or INIT initiates a device reset. In read mode, RST or INIT low deselects the
memory, places the output drivers in a high-impedance state, and turns off all internal circuits.
RST or INIT must be held low for the minimum specified t
operations). The device resets to read array mode upon return from reset, and all Sector Lock-
ing Registers are reset to their default (write-locked) state. Since all Sector Locking Registers
are reset, all sectors in the memory array are set to the write-locked status regardless of their
locked state prior to reset.
A reset recovery time (t
face) is required from RST or INIT switching back high until writes to the CUI are recognized.
A reset latency will occur if a reset procedure is performed during a programming or erase
operation.
During sector erase or program, driving RST or INIT low will abort the operation underway in
addition to causing a reset latency. Memory contents being altered are no longer valid since
the data may be partially erased or programmed.
It is important to assert RST or INIT during system reset. When the system comes out of reset,
it will expect to read from the memory array of the device. If a system reset occurs with no
FWH/LPC device reset (this will be hardware dependent), it is possible that proper CPU initial-
ization will not occur (the FWH/LPC memory may be providing status information instead of
memory array data).
Sectors in the memory array can be protected from program and erase operations using a
hardware controlled method and/or a software (register-based) controlled method.
Two pins are available to provide hardware write protection capabilities. The Top Boot Sector
Lock (TBL) pin, when held low, prevents program and sector erase operations to the top sec-
tor of the device (sector 10) where critical code can be stored. When operating in FWH mode,
the TBL pin is also used to protect sectors 9, 8, and 7 against program and erase operations.
In addition, when operating in LPC mode, the TBL pin has the flexibility to provide erase
PHFV
Table 7-4
using the FWH/LPC interface and t
and
Table
7-8) and no internal Flash operation will be
PLPH
time (FWH/LPC and A/A Mux
PHAV
using the A/A Mux inter-
AT49LH004
17