AT49LH004-33TC Atmel, AT49LH004-33TC Datasheet - Page 13

• Manufacturer Part Number: AT49LH004-33TC
• Description: IC FLASH 4MBIT 33MHZ 40TSOP
• Manufacturer: Atmel

Specifications of AT49LH004-33TC

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.6.3
7.6.4
7.6.5
7.6.6
7.7
3383D–FLASH–6/05
LPC Read Cycle
MADDR (Memory Address) Field
Additional Fields for LPC Memory Cycles
TAR (Turn-around) Field
SYNC (Synchronize) Field
This is an 8-clock field that is used to provide a 32-bit (A31 - A0) memory address. The
32 address bits allow for the provisioning to access up to 4 GB of memory space.
The AT49LH004 only decodes the last six MADDR nibbles (A23 - A0) and ignores address
bits A31 - A24. Address bit A23 is used to determine whether reads or writes to the device will
be directed to the memory array (A23 = 1) or to the register space (A23 = 0).
Unlike FWH memory cycles, LPC cycles do not use an IDSEL field to determine which LPC
device in the system is being selected. Instead, the strapping values on the ID[3:0] pins are
compared against address bits A22 - A19 in the MADDR field. For the actual comparison, the
strapped values are internally inverted. For example, if ID3 was strapped to GND, a logical
value of 1 would be compared against address bit A22. If the inverted states of the ID[3:0] pins
match with address bits A22 - A19, then the device will continue to decode the rest of cycle
(see LPC Multiple Device Selection for mode details).
Addresses are transferred to the device with the most significant nibble first.
Additional fields are required to complete an LPC read or write cycle. The placement of these
fields, in addition to the data field, depends on whether the cycle is an LPC read or write. The
LPC Read Cycle and LPC Write Cycle sections detail the order of the various fields.
This 2-clock field is driven by the master when it is turning control over to the LPC memory
device, and it is driven by the LPC device when it is turning control back over to the master.
On the first clock of the TAR field, the master or LPC device drives the FWH/LAD[3:0] lines to
1111b. On the second clock, the master or LPC device puts the FWH/LAD[3:0] lines into a
high-impedance state.
This field is used to add wait-states for an access. It can be several clocks in length. On target
cycles, this field is driven by the LPC memory device. If the LPC device needs to assert wait-
states, it does so by driving a “wait” SYNC value of 0101b on the FWH/LAD[3:0] pins until it is
ready. When ready, the device will drive a “ready” SYNC value of 0000b on the FWH/LAD[3:0]
lines. Valid values for the SYNC field are shown in
Table 7-6.
LPC read cycles are used to read data from the memory array, the Sector Locking Registers,
the GPI register, the Status Register, and the product ID information. Upon initial device
power-up or after exiting from a reset condition, the device will automatically default to the
read array mode.
Valid LPC read cycles begin with a START field of 0000b and a CYCTYPE + DIR field of
010xb being sent to the device. Following the MADDR field, a 2-clock TAR field must be sent
SYNC Value
0000b
0101b
Valid SYNC Values
SYNC Type
RSYNC (Ready SYNC) – Synchronization has been achieved with no error.
WSYNC (Wait SYNC) – Device is indicating wait-states (also referred to as
short-sync).
Table
7-6.
AT49LH004
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