AT45DB041D-SSU Atmel, AT45DB041D-SSU Datasheet - Page 53

• Manufacturer Part Number: AT45DB041D-SSU
• Description: IC FLASH 4MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB041D-SSU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 4M (2048 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Density: 4Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Architecture: Sectored
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 8
• Memory Configuration: 2048 Pages X 256 Bytes
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28. Revision History
3595P–DFLASH–09/09
Revision Level – Revision Date
A – October 2005
B – March 2006
C – June 2006
D – July 2006
E – August 2006
F – November 2006
G – February 2007
H – March 2007
I – April 2007
J – August 2007
K – December 2007
L – April 2008
M – February 2009
N – March 2009
O - April 2009
P - Sept 2009
History
Initial Release
Added “Preliminary”.
Added text, in “Programming the Configuration Register”, to
indicate that power cycling is required to switch to “power of 2” page
size after the opcode enable has been executed.
Added “Legacy Commands” table.
Corrected typographical errors.
Corrected typographical errors.
Added errata regarding Chip Erase.
Removed “Preliminary”.
Removed RDY/BUSY pin references.
Changed page size description from 512 to 256 in
Changed page size description from 528 to 264 in
Added additional text for “power of 2” binary page size option.
Removed SER/BYTE statement from SI and SO pin descriptions in
Table
Changed the number of don’t care bits from 17 to 16 for sector 1-15
erase in
Corrected the density code description from 16-Mbit to 4-Mbit in
Section
Changed A16 address bit for opcode 7Ch from “x” to “A” in
15-6.
Chagned PA8 address bit for opcode 7Ch from “x” to “P” in
15-7.
Changed t
Changed t
Changed t
Changed Note 1 on page 14 from “0 through 15” to “0 through 7”.
The Chip Erase command is supported on devices with date code
0810 and later.
Added Chip Erase time.
Added part nuber ordering code details for suffixes SL954/955.
Added ordering code detail.
Changed t
Changed Deep Power-Down Current values
Updated Absolute Maximum Ratings
Removed Chip Erase Errata
Pg50: replace package drawing as per the attached
- Increased typical value from 5 µA to 15 µA.
- Increased maximum value from 15 µA to 25 µA.
2-1.
14.1.2.
Section
XFR
VCSL
RDPD
DIS
(Typ and Max) to 27 ns and 35 ns, respectively.
and t
from 50 µs to 70 µs.
from 30 µs to 35 µs.
7.6.
COMP
values from 400 µs to 200 µs.
AT45DB041D
Table
Table
15-6.
15-7.
Table
Table
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