AT45DB041D-SU Atmel, AT45DB041D-SU Datasheet - Page 24

• Manufacturer Part Number: AT45DB041D-SU
• Description: IC FLASH 4MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB041D-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 4M (2048 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Density: 4Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC EIAJ
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Architecture: Sectored
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 264 B
• Current, Input, Leakage: 1 μA
• Current, Operating: 10 mA (Read), 12 mA (Program/Erase)
• Current, Output, Leakage: 1
• Data Retention: 20 yrs.
• Temperature, Operating: -40 to +85 °C
• Time, Access: 6 ns
• Time, Address Hold: 5
• Time, Address Setup: 5
• Time, Fall: 6.8 ns
• Time, Rise: 6.8 ns
• Voltage, Input, High: 1.89 to 2.52 V
• Voltage, Input, Low: 0.81 to 1.08 V
• Voltage, Output, High: 2.5 to 3.4 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.7 to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12. Deep Power-down
12.1
24
Resume from Deep Power-down
AT45DB041D
After initial power-up, the device will default in standby mode. The Deep Power-down command
allows the device to enter into the lowest power consumption mode. To enter the Deep Power-
down mode, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode
of B9H command must be clocked in via input pin (SI). After the last bit of the command has
been clocked in, the CS pin must be de-asserted to initiate the Deep Power-down operation.
After the CS pin is de-asserted, the will device enter the Deep Power-down mode within the
maximum t
are ignored except for the Resume from Deep Power-down command.
Figure 12-1. Deep Power-down
The Resume from Deep Power-down command takes the device out of the Deep Power-down
mode and returns it to the normal standby mode. To Resume from Deep Power-down mode, the
CS pin must first be asserted and an opcode of ABH command must be clocked in via input pin
(SI). After the last bit of the command has been clocked in, the CS pin must be de-asserted to
terminate the Deep Power-down mode. After the CS pin is de-asserted, the device will return to
the normal standby mode within the maximum t
the t
down, the device will return to the normal standby mode.
Figure 12-2. Resume from Deep Power-Down
Command
Deep Power-down
Command
Resume from Deep Power-down
RDPD
time before the device can receive any commands. After resuming form Deep Power-
EDPD
time. Once the device has entered the Deep Power-down mode, all instructions
CS
CS
SI
SI
Each transition
represents 8 bits
Each transition
represents 8 bits
Opcode
Opcode
RDPD
time. The CS pin must remain high during
Opcode
B9H
Opcode
ABH
3595P–DFLASH–09/09