CY7C1383B-100AC Cypress Semiconductor Corp, CY7C1383B-100AC Datasheet

Page 1

... Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. SRAMs integrate All inputs and outputs of the CY7C1381B and the CY7C1383B are JEDEC-standard JESD8-5-compatible. 117 MHz 100 MHz 7.5 8 ...

Page 2

... BYTEWRITE REGISTERS D DQc[23:16],DP2 Q BYTEWRITE REGISTERS D DQb[15:8],DP1 Q BYTEWRITE REGISTERS D DQa[7:0],DP0 Q BYTEWRITE REGISTERS D ENABLE Q CE REGISTER CLK SLEEP CONTROL CY7C1381B CY7C1383B 20 1M × 18 MEMORY ARRAY 18 18 INPUT REGISTERS CLK DQ [15:0] DP [1:0] 19 512K × 36 MEMORY ARRAY 36 36 INPUT REGISTERS CLK DQ [31:0] DP ...

Page 3

... DQa DPb 24 57 DQa DQa VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ DQa DQa DPa CY7C1381B CY7C1383B VDDQ 76 VSSQ DPa 73 DQa 72 DQa 71 VSSQ 70 VDDQ 69 DQa 68 DQa 67 VSS CY7C1383B 66 NC (1M × 18) 65 VDD DQa 62 DQa 61 VDDQ 60 VSSQ 59 DQa 58 DQa VSSQ 54 VDDQ Page ...

Page 4

... U V DDQ Document #: 38-05196 Rev. ** 119-ball BGA CY7C1381B (512K × 36 ADSP A A ADSC DQP ADV CLK BWE DQP MODE 64M A A TMS TDI TCK CY7C1383B (1M × 18 ADSP A A ADSC ADV CLK BWE DQP MODE 32M TMS TDI TCK CY7C1381B CY7C1383B DDQ ...

Page 5

... DPc DQc DQc V E DQc DQc V F DQc DQc V G DQc DQc DQd DQd V K DQd DQd V L DQd DQd V M DQd DQd V N DPd 64M R MODE 32M CY7C1383B (1M × 18) – 11 × 15 FBGA DQb DQb DQb DQb DQb DQb DQb DQb ...

Page 6

... DPa–DPd are placed in a three-state condition. DQ a,b,c and d are eight-bits wide. DP a,b,c and d are one-bit wide. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA only). CY7C1381B CY7C1383B , are also [1:0] is deasserted HIGH ...

Page 7

... Ground for the core of the device. Should be connected to ground of the system. Power supply for the I/O circuitry. Ground for the I/O circuitry. Should be connected to ground of the system. No connects. Pins are not internally connected. No connects. Reserved for address expansion. Pins are not internally connected. CY7C1381B CY7C1383B Page ...

Page 8

... Asserting the Byte Write Enable (BWE) input with the selected Byte Write (BW for CY7C1381B and BW a,b,c,d CY7C1383B) input will selectively Write to only the desired bytes. Bytes not selected during a byte Write operation will remain unaltered. All I/Os are three-stated during a byte Write. Because the CY7C1381B/CY7C1383B is a common I/O device, the OE must be deasserted HIGH before presenting data to the DQx inputs ...

Page 9

... OE is asynchronous and is not sampled with the clock rise masked internally during Write cycles. During a Read cycle High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active. Document #: 38-05196 Rev. ** Test Conditions ZZ < V – 0. < V – ADSP CY7C1381B CY7C1383B Min. Max CYC 2t CYC ADSC ADV ...

Page 10

... Write Bytes 3, 1 Write Bytes Write Bytes 3, 2 Write Bytes Write Bytes Write All Bytes Write All Bytes Function (CY7C1383B) Read Read Write Byte 0 – DQa and DPa Write Byte 1 – DQb and DPb Write All Bytes Write All Bytes Document #: 38-05196 Rev. ** ...

Page 11

... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1381B/CY7C1383B incorporates a serial boundary scan TAP in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1–1900, but does not have the set of functions required for full 1149.1 compliance. These ...

Page 12

... TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1381B CY7C1383B Page ...

Page 13

... TEST-LOGIC/ 0 IDLE Note: 4. Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05196 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1381B CY7C1383B 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...

Page 14

... TAP Controller [5, 6] Over the Operating Range Test Conditions 100 8 100 A OL GND DDQ / 2; undershoot: V (AC) < 0.5V for t < t TCYC IL TCYC CY7C1381B CY7C1383B 0 Selection Circuitry Min. Max. 2.4 V – 0 0.5 5 /2; power-up: V < 2.6V and V < 2.4V and TDO ...

Page 15

... Test conditions are specified using the load in TAP AC test conditions ns. Document #: 38-05196 Rev. ** [7, 8] Over the Operating Range Description CY7C1381B CY7C1383B Min. Max Unit 100 ns 10 MHz 40 ns ...

Page 16

... TAP Timing and Test Conditions 1.25V 50 TDO GND (a) Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-05196 Rev. ** ALL INPUT PULSES 3.3V 1.50V TCYC t TMSS t TMSH t TDIS t TDIH t t TDOV TDOX CY7C1381B CY7C1383B Page ...

Page 17

... Do Not Use. This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1381B CY7C1383B Description Reserved for version number. Defines depth of SRAM. 512K or 1M Defines with of the SRAM. ×36 or ×18 Reserved for future use ...

Page 18

... DQd 2P 24 OE# DQd 1K 25 BWE# DQd 2L 26 GW# DQd 2N 27 CLK DQd MODE 3R 29 BWa BWb CE DQb CY7C1381B CY7C1383B Signal Bump Signal Name ID Bit # Name 2R 36 DQb 2T 37 DQb 3T 38 DQb DQb 3B 41 DQb 5B 42 DQb 7P 43 DQb 6N 44 DQb 6L 45 MODE ...

Page 19

... IN DDQ 1/t 12-ns cycle, 83 MHz MAX CYC Max Device All speeds DD Deselected, V > < CY7C1381B CY7C1383B Ambient [10] Temp V DD 0°C to +70°C 3.3V 2.5V – 5% –5% / +10% 3.3V + 10% –40°C to +85°C Min. Max. 3.135 3.63 2.375 3.63 = 2.5V 2.0 = 3.3V 2.4 = 2.5V ...

Page 20

... Input waveform should have a slew rate of 1 V/ns. Document #: 38-05196 Rev. ** Test Conditions MHz 3.3V 3.3V DDQ R = 1667 V DDQ OUTPUT 1538 INCLUDING JIG AND SCOPE (b) Test Conditions CY7C1381B CY7C1383B Max [12] ALL INPUT PULSES V DD 90% 10% GND < 1V/ns ( (Junction to Ambient) (Junction to Case) 41.54 6.33 44.51 2.38 ...

Page 21

... EOLZ CHZ CLZ CY7C1381B CY7C1383B –100 –83 Min. Max. Min. Max. Unit 10.0 12.0 2.5 3.0 2.5 3.0 1.5 1.5 0.5 0.5 8.5 10.0 1 ...

Page 22

... WE is the combination of BWE, BWx, and GW to define a Write cycle (see Write Cycle Descriptions table). 17. WDx stands for Write Data to Address X. Document #: 38-05196 Rev. ** Burst Write ADSP ignored with CE inactive CL 1 WD2 masks ADSP Undefined Don’t Care CY7C1381B CY7C1383B Pipelined Write Unselected ADSC initiated Write WD3 Unselected with CE 2 High Page ...

Page 23

... Note: 18. RDx stands for Read Data from Address X. Document #: 38-05196 Rev. ** Burst Read ADSP ignored with Suspend Burst ADH masks ADSP DOH CLZ = Don’t Care = Undefined CY7C1381B CY7C1383B Unselected Pipelined Read inactive 1 ADSC initiated Read RD3 Unselected with CHZ Page ...

Page 24

... ADH t t ADVH ADVS t WES ADSP ignored with CE HIGH Q(B) (B+2) (B+1) (B+3) and CE . All chip selects need to be active in order to select Undefined = Don’t Care CY7C1381B CY7C1383B ADH t CEH t CEH t WEH t EOHZ D(C) (C+1) (C+2) (C+3) tDOH tCHZ Q(D) Page ...

Page 25

... CE . All chip selects need to be active in order to select the device Document #: 38-05196 Rev. ** [19, 20 CYC CH t ADH t WES ADSP ignored with CE HIGH Out = Don’t Care = Undefined CY7C1381B CY7C1383B t CL WD1 WD2 WD3 WD4 t CEH t WEH D( DOH t CHZ Back-to-Back Writes ...

Page 26

... Switching Waveforms (continued) OE Switching Waveforms ZZ Mode Timing [19, 21] CLK ADSP HIGH ADSC CE 1 LOW CE 2 HIGH I/Os Note: 21. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05196 Rev EOHZ Three-State I/Os t EOLZ t ZZS I (active CCZZ Three-state CY7C1381B CY7C1383B t EOV t ZZREC Page ...

Page 27

... Ordering Information Speed (MHz) Ordering Code 117 CY7C1381B-117AC CY7C1383B-117AC CY7C1381B-117BGC CY7C1383B-117BGC CY7C1381B-117BZC CY7C1383B-117BZC 100 CY7C1381B-100AC CY7C1383B-100AC CY7C1381B-100BGC CY7C1383B-100BGC CY7C1381B-100BZC CY7C1383B-100BZC 83 CY7C1381B-83AC CY7C1383B-83AC CY7C1381B-83BGC CY7C1383B-83BGC CY7C1381B-83BZC CY7C1383B-83BZC 100 CY7C1381B-100AI CY7C1383B-100AI CY7C1381B-100BGI CY7C1383B-100BGI CY7C1381B-100BZI CY7C1383B-100BZI 83 CY7C1381B-83AI CY7C1383B-83AI CY7C1381B-83BGI CY7C1383B-83BGI CY7C1381B-83BZI CY7C1383B-83BZI Shaded areas contain advance information. ...

Page 28

... Pin Configurations 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 Document #: 38-05196 Rev. ** CY7C1381B CY7C1383B Page ...

Page 29

... Pin Configurations (continued) Document #: 38-05196 Rev. ** 119-lead FBGA (14 × 22 × 2.4 mm) BG119 CY7C1381B CY7C1383B Page ...

Page 30

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 165-ball FBGA (13 × 15 × 1.2 mm) BB165A CY7C1381B CY7C1383B Page ...

Page 31

... Revision History Document Title: CY7C1381B/CY7C1383B 512K x36/1M x18 Flow-Thru SRAM Document Number: 38-05196 ISSUE REV. ECN NO. DATE ** 112032 12/09/01 Document #: 38-05196 Rev. ** ORIG. OF CHANGE DESCRIPTION OF CHANGE DSG Change from Spec number: 38-01077 to 38-05196 CY7C1381B CY7C1383B Page ...