CY7C131-25JC Cypress Semiconductor Corp, CY7C131-25JC Datasheet

IC SRAM 8KBIT 25NS 52PLCC

CY7C131-25JC

Manufacturer Part Number
CY7C131-25JC
Description
IC SRAM 8KBIT 25NS 52PLCC
Manufacturer
Cypress Semiconductor Corp
Datasheets

Specifications of CY7C131-25JC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
8K (1K x 8)
Speed
25ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-PLCC
Density
8Kb
Access Time (max)
25ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
10b
Package Type
PLCC
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
170mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Word Size
8b
Number Of Words
1K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1193

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C131-25JC
Manufacturer:
CYP
Quantity:
5 510
Part Number:
CY7C131-25JC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C131-25JC
Manufacturer:
CYP
Quantity:
669
Part Number:
CY7C131-25JC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CY7C131-25JC
Quantity:
91
Features
s
Notes:
Logic Block Diagram
Cypress Semiconductor Corporation
1.
2.
• True Dual-Ported memory cells which allow simulta-
• 1K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: I
• Fully asynchronous operation
• Automatic power-down
• Master CY7C130/CY7C131 easily expands data bus
• BUSY output flag on CY7C130/CY7C131; BUSY input
• INT flag for port-to-port communication
• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC and
• Pin-compatible and functionally equivalent to
neous reads of the same memory location
width to 16 or more bits using slave CY7C140/CY7C141
on CY7C140/CY7C141
52-pin TQFP
IDT7130/IDT7140
CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor
CY7C140/CY7C141 (Slave): BUSY is input.
Open drain outputs: pull-up resistor required
BUSY
INT
R/W
I/O
I/O
CE
OE
A
A
L
L
7L
0L
[1]
9L
[2]
0L
L
L
L
DECODER
ADDRESS
CC
R/W
CE
OE
= 90 mA (max.)
L
L
L
CONTROL
I/O
(7C130/7C131 ONLY)
INTERRUPT LOGIC
ARBITRATION
MEMORY
ARRAY
LOGIC
AND
3901 North First Street
CONTROL
I/O
DECODER
ADDRESS
CE
OE
R/W
R
R
R
Functional Description
The
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/ CY7C131 can be utilized as either a
standalone 8-bit dual-port static RAM or as a master dual-port
RAM in conjunction with the CY7C140/CY7C141 slave du-
al-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). Two flags are
provided on each port, BUSY and INT. BUSY signals that the
port is trying to access the same location currently being ac-
cessed by the other port. INT is an interrupt flag indicating that
data has been placed in a unique location (3FF for the left port
and 3FE for the right port). An automatic power-down feature
is controlled independently on each port by the chip enable
(CE) pins.
The CY7C130 and CY7C140 are available in 48-pin DIP. The
CY7C131 and CY7C141 are available in 52-pin PLCC and
PQFP.
1K x 8 Dual-Port Static Ram
CY7C130/CY7C131/CY7C140
San Jose
INT
A
A
R/W
CE
OE
I/O
I/O
BUSY
9R
0R
R
R
7R
0R
R
C130-1
R
[2]
R
May 1989 – Revised March 27, 1997
CY7C130/CY7C131
CY7C140/CY7C141
CA 95134
BUSY
R/W
Pin Configurations
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INT
GND
CE
OE
A
A
A
A
A
A
A
A
A
A
0L
1L
2L
3L
4L
5L
6L
7L
0L
1L
2L
3L
4L
5L
6L
7L
8L
9L
L
L
L
L
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Top View
and
7C130
7C140
DIP
fax id: 5200
CY7C141
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
408-943-2600
V
CE
R/W
INT
OE
A
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
BUSY
CC
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
C130-2
R
R
7R
6R
5R
4R
3R
2R
1R
0R
R
R
R
are

Related parts for CY7C131-25JC

CY7C131-25JC Summary of contents

Page 1

... R/W L [2] INT L Notes: 1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor CY7C140/CY7C141 (Slave): BUSY is input. 2. Open drain outputs: pull-up resistor required s Cypress Semiconductor Corporation Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 high-speed CMOS dual-port static RAMs. Two ports are provided permitting independent access to any location in memory ...

Page 2

... Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Range Commercial Industrial [5] Military 2 CY7C130/CY7C131 CY7C140/CY7C141 PQFP Top View 52 5150 7C131 33 7C141 1415 C130-4 7C130-35 7C130-45 7C131-35 7C131-45 ...

Page 3

... CC Mil > V – 0.2V CC < 0.2V, IN [10] and using AC Test Waveforms input levels of GND to 3V. RC Test Conditions MHz 5. CY7C130/CY7C131 CY7C140/CY7C141 [3] 7C130-30 7C130-35 7C130-45,55 7C131-25,30 7C131-35 7C131-45,55 7C140-30 7C140-35 7C140-45,55 7C141-25,30 7C141-35 7C141-45,55 Min. Max. Min. Max. Min. Max. Unit 2 ...

Page 4

... HZCE LZCE = 5pF as in part ( Test Loads . Transition is measured ±500 mV from steady state voltage CY7C130/CY7C131 CY7C140/CY7C141 BUSY OR INT BUSY Output Load ALL INPUT PULSES (CY7C130/CY7C131 ONLY) 90% 90% 10% 5ns [3] 7C130-25 7C130-30 7C131-25 7C131-30 [3,4] 7C140-25 7C140-30 7C141-25 7C141-30 Max. ...

Page 5

... CE LOW to Power- HIGH to Power-Down PD [6,11] (continued) 7C131-15 7C141-15 Min. Max. [16] [16 Note Note [16] [16] [16] [6,11] 7C130-35 7C131-35 7C140-35 7C141-35 Min. Max. 35 [12] 0 [12] [12 [9] 0 [9] 5 CY7C130/CY7C131 CY7C140/CY7C141 [3] 7C130-25 7C130-30 7C131-25 7C131-30 [3,4] 7C140-25 7C140-30 7C141-25 7C141-30 Min. Max. Min. Max Note Note ...

Page 6

... R/W is HIGH for read cycle. 20. Device is continuously selected and [6,11] (continued) 7C130-35 7C131-35 7C140-35 7C141-35 Min. Max [16 [16 Note 18 Note [16] 25 [16] 25 [16] 25 Either Port Address Access CY7C130/CY7C131 CY7C140/CY7C141 7C130-45 7C130-55 7C131-45 7C131-55 7C140-45 7C140-55 7C141-45 7C141-55 Min. Max. Min. Max. Unit ...

Page 7

... Switching Waveforms (continued) [19, 21] Read Cycle No LZOE t LZCE DATA OUT [20] Read Cycle No.3 Read with BUSY, Master: CY7C130 and CY7C131 ADDRESS R R INR ADDRESS L BUSY L DOUT L Write Cycle No.1 (OE Three-States Data I/Os - Either Port) ADDRESS R/W DATA HZOE D OUT Notes: 21. Address valid prior to or coincident with CE transition LOW. ...

Page 8

... If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state [16, 23] Either Port SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE ADDRESS MATCH BLC ADDRESS MATCH BLC 8 CY7C130/CY7C131 CY7C140/CY7C141 LZWE C130-11 BHC C130-12 BHC C130-13 ...

Page 9

... Left Address Valid First: ADDRESS MATCH ADDRESS ADDRESS R BUSY R Right Address Valid First: ADDRESS MATCH ADDRESS ADDRESS L BUSY L Busy Timing Diagram No. 3 Write with BUSY (Slave:CY7C140/CY7C141 BUSY ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA t PWE 9 CY7C130/CY7C131 CY7C140/CY7C141 C130-14 C130- C130-16 ...

Page 10

... Right Side Sets INT L ADDR R t INS INT L Left Side Clears INT L ADDR R INT WRITE 3FF EINS t WINS EINR t WC WRITE 3FE EINS t WINS EINR 10 CY7C130/CY7C131 CY7C140/CY7C141 t RC READ 3FF t INT t OINR C130- READ 3FE t INR t OINR C130-17 C130-18 C130-20 ...

Page 11

... AMBIENT TEMPERATURE ( C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4.5V CC 5 5.0 0 200 400 600 800 CAPACITANCE (pF) 11 CY7C130/CY7C131 CY7C140/CY7C141 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 =5. = 125 0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs.OUTPUT VOLTAGE ...

Page 12

... CY7C130-30PC CY7C130-30PI 35 CY7C130-35PC CY7C130-35PI CY7C130-35DMB 45 CY7C130-45PC CY7C130-45PI CY7C130-45DMB 55 CY7C130-55PC CY7C130-55PI CY7C130-55DMB Speed Package (ns) Ordering Code 15 CY7C131-15JC CY7C131-15NC 25 CY7C131-25JC CY7C131-25NC CY7C131-25JI CY7C131-25NI 30 CY7C131-30JC CY7C131-30NC CY7C131-30JI 35 CY7C131-35JC CY7C131-35NC CY7C131-35JI CY7C131-35NI 45 CY7C131-45JC CY7C131-45NC CY7C131-45JI CY7C131-45NI 55 CY7C131-55JC CY7C131-55NC CY7C131-55JI CY7C131-55NI Shaded area contains preliminary information. ...

Page 13

... Plastic Leaded Chip Carrier N52 52-Pin Plastic Quad Flatpack J69 52-Lead Plastic Leaded Chip Carrier N52 52-Pin Plastic Quad Flatpack J69 52-Lead Plastic Leaded Chip Carrier N52 52-Pin Plastic Quad Flatpack 13 CY7C130/CY7C131 CY7C140/CY7C141 Operating Range Commercial Industrial Commercial Industrial Military Commercial Industrial Military ...

Page 14

... MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups Max SB1 SB2 SB3 SB4 CY7C130/CY7C131 CY7C140/CY7C141 Switching Characteristics Parameter Subgroups READ CYCLE 10 10 10, 11 ACE 10, 11 DOE WRITE CYCLE 10 10, 11 SCE 10, 11 PWE 10 10 Parameter Subgroups BUSY/INTERRUPT TIMING 10, 11 BLA 10, 11 ...

Page 15

... Package Diagrams 48-Lead (600-Mil) Sidebraze DIP D26 52-Lead Plastic Leaded Chip Carrier J69 15 CY7C130/CY7C131 CY7C140/CY7C141 ...

Page 16

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-Lead (600-Mil) Molded DIP P25 CY7C130/CY7C131 CY7C140/CY7C141 ...

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