CY7C146-25JC Cypress Semiconductor Corp, CY7C146-25JC Datasheet - Page 4

IC SRAM 16KBIT 25NS 52PLCC

CY7C146-25JC

Manufacturer Part Number
CY7C146-25JC
Description
IC SRAM 16KBIT 25NS 52PLCC
Manufacturer
Cypress Semiconductor Corp
Datasheets

Specifications of CY7C146-25JC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
16K (2K x 8)
Speed
25ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-PLCC
Density
16Kb
Access Time (max)
25ns
Sync/async
Asynchronous
Architecture
SDR
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
22b
Package Type
PLCC
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
170mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Word Size
8b
Number Of Words
2K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1202

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C146-25JC
Manufacturer:
CYPRESS
Quantity:
1 980
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Manufacturer:
CY
Quantity:
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CY7C146-25JC
Manufacturer:
Cypress Semiconductor Corp
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Part Number:
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Quantity:
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Part Number:
CY7C146-25JC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document #: 38-06031 Rev. *A
AC Test Loads and Waveforms
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
Shaded areas contain preliminary information.
Notes:
10. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
12. At any given temperature and voltage condition for any given device, t
13. t
14. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
11. AC test conditions use V
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
Parameter
I
a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
OL
LZCE
Equivalent to:
OUTPUT
/I
OH,
, t
LZWE
and 30-pF load capacitance.
INCLUDING
5V
[14]
, t
JIG AND
HZOE
SCOPE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
R/W Pulse Width
Data Set-up to Write End
Data Hold from Write End
OUTPUT
30 pF
, t
LZOE,
t
OH
HZCE,
TH ÉVENIN EQUIVALENT
(a)
R1893
= 1.6V and V
and t
Description
HZWE
R2
347
250
Over the Operating Range (Speeds -15, -25, -30)
[9, 12]
[9, 12]
[9, 12, 13]
OL
[9, 12, 13]
are tested with C
= 1.4V.
[11]
[9]
[11]
[11]
[9]
1.4V
OUTPUT
L
= 5pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
INCLUDING
5V
JIG AND
SCOPE
5 pF
HZCE
Min.
GND
3.0V
15
15
12
12
12
10
7C136-15
0
3
3
0
2
0
0
is less than t
7C146-15
R1893
(b)
< 5 ns
Max.
10%
LZCE
15
15
10
10
10
15
R2
347
[3]
and t
ALL INPUT PULSES
HZOE
90%
Min.
25
25
20
20
15
15
7C132-25
0
3
5
0
2
0
0
is less than t
7C136-25
7C142-25
7C146-25
[5, 10]
Max.
25
25
15
15
15
25
LZOE
(CY7C132/CY7C136 Only)
[3]
BUSY
CY7C132/CY7C136
CY7C142/CY7C146
OR
INT
.
BUSY Output Load
90%
10%
Min.
30
30
25
25
25
15
< 5 ns
0
3
5
0
2
0
0
7C132-30
7C136-30
7C142-30
7C146-30
5V
281
30 pF
Max.
30
30
20
15
15
25
Page 4 of 17
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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